Abstract: A programmable read-only-memory (PROM) element is disclosed in which an N-type epitaxial layer, grown on a P-type substrate with an N+ buried layer therebetween, has a P-type anode region formed in a surface portion thereof. An N-type poly-silicon layer is formed on the surface of the anode region, generally within an aperture in an insulating layer, with the dopant of the poly-silicon layer being diffused downwardly into the anode region to form a shallow N-type cathode region. A metal layer is deposited on the surface of the poly-silicon layer over the anode region, and a low resistivity path is provided to the buried layer. To program the memory element, a positive potential is applied to the metal layer relative to the buried layer to break down the barrier between the cathode and anode regions. As the reverse current flow heats the poly-silicon, the metal alloys through the poly-silicon and the cathode region, and shorts to the anode region.

Abstract: A TTL logic circuit employing single emitter PNP input transistors instead of a multi-emitter input stage, in order to reduce loading on input drive devices. The circuit features a logic swing of 1.6 volts centered on a circuit threshold of 1.6 volts with the logic 0 and logic 1 levels being internally clamped with p-n diode junctions to prevent transistor saturation and improve transistor switching speeds over those normally obtained using Schottky diode clamping techniques. The circuit output incorporates a Darlington stage and provides a logic 1 drive capability permitting the circuit to drive a terminated signal line having a low characteristic impedance, typically 50 ohms while maintaining a logic 1 level above 2.0 volts at 25.degree. C. Use of ion implantation techniques to define the isolation, emitter and base regions as well as the p-n diode junctions permits smaller device geometries and high F.sub.T transistors capable of high speed switching.