Patents by Inventor Earl J. Wight

Earl J. Wight has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Crosstalk aware decoding for a data bus
    Patent number: 9632961
    Abstract: Techniques for decoding encoded data are described herein. An example of a device in accordance with the present techniques includes a receiving signaling module coupled to a plurality of signal lines. The signaling module includes a receiver to receive a plurality of encoded line voltages or currents on the plurality of signal lines of a bus, wherein each one of the plurality of encoded line voltages corresponds to a weighted sum of data. The signaling module includes a comparator to determine the voltage level of each line at a unit interval and convert the voltage level to a digital value. The signaling module includes a lookup table correlating the digital value with a digital bit stream.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: April 25, 2017
    Assignee: INTEL CORPORATION
    Inventors: Olufemi B. Oluwafemi, Stephen H. Hall, Jason A. Mix, Earl J. Wight, Chaitanya Sreerama, Michael W. Leddige, Paul G. Huray
  • CROSSTALK AWARE DECODING FOR A DATA BUS
    Publication number: 20140181358
    Abstract: Techniques for decoding encoded data are described herein. An example of a device in accordance with the present techniques includes a signaling module with a receiver, quantizer, and arithmetic circuit. The receiver receives a plurality of encoded line voltages or currents on a plurality of signal lines. The quantizer determines signal levels of each of the plurality of signal lines at a unit interval. The arithmetic circuit provides a plurality of digital output bits of the decoder based on the signal levels. Each one of the digital output bits is a mathematical combination of all of the signal levels.
    Type: Application
    Filed: December 28, 2013
    Publication date: June 26, 2014
    Inventors: Chaitanya Sreerama, Stephen H. Hall, Olufemi OLUWAFEMI, JASON A. Mix, Michael Leddige, Earl J. Wight, Antonio Zenteno Ramirez
  • CROSSTALK AWARE DECODING FOR A DATA BUS
    Publication number: 20140181348
    Abstract: Techniques for decoding encoded data are described herein. An example of a device in accordance with the present techniques includes a receiving signaling module coupled to a plurality of signal lines. The signaling module includes a receiver to receive a plurality of encoded line voltages or currents on the plurality of signal lines of a bus, wherein each one of the plurality of encoded line voltages corresponds to a weighted sum of data. The signaling module includes a comparator to determine the voltage level of each line at a unit interval and convert the voltage level to a digital value. The signaling module includes a lookup table correlating the digital value with a digital bit stream.
    Type: Application
    Filed: March 15, 2013
    Publication date: June 26, 2014
    Inventors: Olufemi B. Oluwafemi, Stephen H. Hall, Jason A. Mix, Earl J. Wight, Chaitanya Sreerama, Michael W. Leddige, Paul G. Huray