Patents by Inventor Earl K. Hunter

Earl K. Hunter has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10211815
    Abstract: An integrated circuit includes a first portion of a stacked ring oscillator coupled between a first supply voltage node and a common node, wherein the first supply voltage node provides a local supply voltage for the first portion and the common node provides a local ground for the first portion. The integrated circuit includes a second portion of the stacked ring oscillator coupled between the common node and a second supply voltage node wherein the common node provides a local supply voltage for the second portion and the second supply voltage node provides a local ground for the second portion. The integrated circuit also includes a voltage divider having a first resistive element coupled between the first supply node and the common node and a second resistive element coupled between the common node and the second supply node.
    Type: Grant
    Filed: April 22, 2016
    Date of Patent: February 19, 2019
    Assignee: NXP USA, Inc.
    Inventors: Earl K. Hunter, Miguel Mendez, Yi Cheng Chang
  • Publication number: 20170310307
    Abstract: An integrated circuit includes a first portion of a stacked ring oscillator coupled between a first supply voltage node and a common node, wherein the first supply voltage node provides a local supply voltage for the first portion and the common node provides a local ground for the first portion. The integrated circuit includes a second portion of the stacked ring oscillator coupled between the common node and a second supply voltage node wherein the common node provides a local supply voltage for the second portion and the second supply voltage node provides a local ground for the second portion. The integrated circuit also includes a voltage divider having a first resistive element coupled between the first supply node and the common node and a second resistive element coupled between the common node and the second supply node.
    Type: Application
    Filed: April 22, 2016
    Publication date: October 26, 2017
    Inventors: Earl K. HUNTER, Miguel MENDEZ, Yi Cheng CHANG
  • Publication number: 20170187399
    Abstract: Embodiments of single-ended and differential output driver circuits include one or more complementary data switch pairs, each coupled to a T-coil. Each complementary data switch pair is coupled between a voltage source and a ground reference node, and each complementary data switch pair includes complementary transistors, each with a control terminal, a first current conducting terminal, and a second current conducting terminal. In each pair, the first current conducting terminals of the complementary transistors are coupled together at an output node, and the control terminals of the complementary transistors are configured to receive an input signal. A T-coil is coupled to the output node, and includes a first coil coupled between the output node and an output terminal, and a second coil coupled between the output node and a termination. A mutual inductance is present between the first and second coils during operation of the output driver circuit.
    Type: Application
    Filed: December 29, 2015
    Publication date: June 29, 2017
    Inventors: Earl K. Hunter, BRYAN D. PREBLE
  • Patent number: 8806418
    Abstract: A method can include generating a first set of sample values for input variables in accordance with a prescribed set of probability distributions, running a set of simulations on an electronic component based upon the first set of sample values, multiplying the standard deviations of the original distributions by a scaling factor ?, generating a second set of sample values for the input variables based on the probability distributions thus generated, and running a set of simulations on the electronic component based on this second set of sample values. The method can also include the generation of Q-Q plots based on the data from the first and second set of simulations and data from a truly normal distribution or the distribution obeyed by the independently varying input parameters; and the use of these plots for assessment of the robustness and functionality of the electronic component.
    Type: Grant
    Filed: June 19, 2013
    Date of Patent: August 12, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Srinivas Jallepalli, Earl K. Hunter, Elie A. Maalouf, Venkataram M. Mooraka, Sanjay R. Parihar