Patents by Inventor Earl Swartzlander
Earl Swartzlander has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10608639Abstract: Memristor-based dividers using memristors-as-drivers (MAD) gates. As a result of employing MAD gates in memristor-based dividers, such as binary non-restoring dividers and SRT dividers, the number of delay steps may be less than half than the number of delay steps required in traditional CMOS implementations of dividers. Furthermore, by using MAD gates, memristor-based dividers can be implemented with less complexity (e.g., fewer memristors and drivers). As a result, by the memristor-based dividers using MAD gates, the speed and complexity of a wide variety of arithmetic operations is improved.Type: GrantFiled: September 4, 2019Date of Patent: March 31, 2020Assignee: Board of Regents, The University of Texas SystemInventors: Earl Swartzlander, Lauren Guckert
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Patent number: 10558431Abstract: Memristor-based multipliers using memristors-as-drivers (MAD) gates. As a result of employing MAD gates in memristor-based multipliers, such as shift-and-add multipliers, Booth multipliers and array multipliers, the number of delay steps may be less than half than the number of delay steps required in traditional CMOS implementations of multipliers. Furthermore, by using MAD gates, memristor-based multipliers can be implemented with less complexity (e.g., fewer memristors and drivers). As a result, by the memristor-based multipliers using MAD gates, the speed and complexity of a wide variety of arithmetic operations is improved.Type: GrantFiled: April 29, 2019Date of Patent: February 11, 2020Assignee: Board of Regents, The University of Texas SystemInventors: Earl Swartzlander, Lauren Guckert
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Publication number: 20200014388Abstract: Memristor-based dividers using memristors-as-drivers (MAD) gates. As a result of employing MAD gates in memristor-based dividers, such as binary non-restoring dividers and SRT dividers, the number of delay steps may be less than half than the number of delay steps required in traditional CMOS implementations of dividers. Furthermore, by using MAD gates, memristor-based dividers can be implemented with less complexity (e.g., fewer memristors and drivers). As a result, by the memristor-based dividers using MAD gates, the speed and complexity of a wide variety of arithmetic operations is improved.Type: ApplicationFiled: September 4, 2019Publication date: January 9, 2020Inventors: Earl Swartzlander, Lauren Guckert
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Patent number: 10447271Abstract: Memristor-based dividers using memristors-as-drivers (MAD) gates. As a result of employing MAD gates in memristor-based dividers, such as binary non-restoring dividers and SRT dividers, the number of delay steps may be less than half than the number of delay steps required in traditional CMOS implementations of dividers. Furthermore, by using MAD gates, memristor-based dividers can be implemented with less complexity (e.g., fewer memristors and drivers). As a result, by the memristor-based dividers using MAD gates, the speed and complexity of a wide variety of arithmetic operations is improved.Type: GrantFiled: April 15, 2019Date of Patent: October 15, 2019Assignee: Board of Regents, The University of Texas SystemInventors: Earl Swartzlander, Lauren Guckert
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Publication number: 20190250885Abstract: Memristor-based multipliers using memristors-as-drivers (MAD) gates. As a result of employing MAD gates in memristor-based multipliers, such as shift-and-add multipliers, Booth multipliers and array multipliers, the number of delay steps may be less than half than the number of delay steps required in traditional CMOS implementations of multipliers. Furthermore, by using MAD gates, memristor-based multipliers can be implemented with less complexity (e.g., fewer memristors and drivers). As a result, by the memristor-based multipliers using MAD gates, the speed and complexity of a wide variety of arithmetic operations is improved.Type: ApplicationFiled: April 29, 2019Publication date: August 15, 2019Inventors: Earl Swartzlander, Lauren Guckert
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Publication number: 20190245542Abstract: Memristor-based dividers using memristors-as-drivers (MAD) gates. As a result of employing MAD gates in memristor-based dividers, such as binary non-restoring dividers and SRT dividers, the number of delay steps may be less than half than the number of delay steps required in traditional CMOS implementations of dividers. Furthermore, by using MAD gates, memristor-based dividers can be implemented with less complexity (e.g., fewer memristors and drivers). As a result, by the memristor-based dividers using MAD gates, the speed and complexity of a wide variety of arithmetic operations is improved.Type: ApplicationFiled: April 15, 2019Publication date: August 8, 2019Inventors: Earl Swartzlander, Lauren Guckert
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Patent number: 10318242Abstract: Memristor-based multipliers using memristors-as-drivers (MAD) gates. As a result of employing MAD gates in memristor-based multipliers, such as shift-and-add multipliers, Booth multipliers and array multipliers, the number of delay steps may be less than half than the number of delay steps required in traditional CMOS implementations of multipliers. Furthermore, by using MAD gates, memristor-based multipliers can be implemented with less complexity (e.g., fewer memristors and drivers). As a result, by the memristor-based multipliers using MAD gates, the speed and complexity of a wide variety of arithmetic operations is improved.Type: GrantFiled: August 28, 2018Date of Patent: June 11, 2019Assignee: Board of Regents, The University of Texas SystemInventors: Earl Swartzlander, Lauren Guckert
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Patent number: 10305484Abstract: Memristor-based dividers using memristors-as-drivers (MAD) gates. As a result of employing MAD gates in memristor-based dividers, such as binary non-restoring dividers and SRT dividers, the number of delay steps may be less than half than the number of delay steps required in traditional CMOS implementations of dividers. Furthermore, by using MAD gates, memristor-based dividers can be implemented with less complexity (e.g., fewer memristors and drivers). As a result, by the memristor-based dividers using MAD gates, the speed and complexity of a wide variety of arithmetic operations is improved.Type: GrantFiled: August 28, 2018Date of Patent: May 28, 2019Assignee: Board of Regents, The University of Texas SystemInventors: Earl Swartzlander, Lauren Guckert
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Publication number: 20190079731Abstract: Memristor-based multipliers using memristors-as-drivers (MAD) gates. As a result of employing MAD gates in memristor-based multipliers, such as shift-and-add multipliers, Booth multipliers and array multipliers, the number of delay steps may be less than half than the number of delay steps required in traditional CMOS implementations of multipliers. Furthermore, by using MAD gates, memristor-based multipliers can be implemented with less complexity (e.g., fewer memristors and drivers). As a result, by the memristor-based multipliers using MAD gates, the speed and complexity of a wide variety of arithmetic operations is improved.Type: ApplicationFiled: August 28, 2018Publication date: March 14, 2019Inventors: Earl Swartzlander, Lauren Guckert
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Publication number: 20190081628Abstract: Memristor-based dividers using memristors-as-drivers (MAD) gates. As a result of employing MAD gates in memristor-based dividers, such as binary non-restoring dividers and SRT dividers, the number of delay steps may be less than half than the number of delay steps required in traditional CMOS implementations of dividers. Furthermore, by using MAD gates, memristor-based dividers can be implemented with less complexity (e.g., fewer memristors and drivers). As a result, by the memristor-based dividers using MAD gates, the speed and complexity of a wide variety of arithmetic operations is improved.Type: ApplicationFiled: August 28, 2018Publication date: March 14, 2019Inventors: Earl Swartzlander, Lauren Guckert
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Patent number: 10171083Abstract: A new lower-power gate design for memristor-based Boolean operations. Such a design offers a uniform cell that is configurable to perform all Boolean operations, including the XOR operation. For example, a circuit to perform the AND operation utilizes a first memristor and a second memristor connected in series. The circuit further includes a switch, where a node of the second memristor is connected to the switch. Furthermore, the circuit includes a third memristor connected to the switch in series, where the switch and the third memristor are connected in parallel to the first and second memristors. Additionally, the first voltage source is connected to the first memristor via a first resistor. In addition, a second voltage source is connected in series to the switch and the third memristor. In such a design, the delay is reduced to a single step and the area is reduced to at most 3 memristors.Type: GrantFiled: December 5, 2016Date of Patent: January 1, 2019Assignee: Board of Regents, The University of Texas SystemInventors: Earl Swartzlander, Lauren Guckert
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Publication number: 20180159536Abstract: A new lower-power gate design for memristor-based Boolean operations. Such a design offers a uniform cell that is configurable to perform all Boolean operations, including the XOR operation. For example, a circuit to perform the AND operation utilizes a first memristor and a second memristor connected in series. The circuit further includes a switch, where a node of the second memristor is connected to the switch. Furthermore, the circuit includes a third memristor connected to the switch in series, where the switch and the third memristor are connected in parallel to the first and second memristors. Additionally, the first voltage source is connected to the first memristor via a first resistor. In addition, a second voltage source is connected in series to the switch and the third memristor. In such a design, the delay is reduced to a single step and the area is reduced to at most 3 memristors.Type: ApplicationFiled: December 5, 2016Publication date: June 7, 2018Inventors: Earl Swartzlander, Lauren Guckert
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Patent number: 9971564Abstract: Memristor-based adders using memristors-as-drivers (MAD) gates. As a result of employing MAD gates in memristor-based adders, such as ripple carry adders, carry select adders, conditional sum adders and carry lookahead adders, the number of delay steps may be less than half than the number of delay steps required in traditional CMOS implementations of adders. Furthermore, by using MAD gates, memristor-based adders can be implemented with less complexity (e.g., fewer memristors and drivers). As a result, by the memristor-based adders using MAD gates, the speed and complexity of a wide variety of arithmetic operations is improved.Type: GrantFiled: February 2, 2018Date of Patent: May 15, 2018Assignee: Board of Regents, The University of Texas SystemInventors: Earl Swartzlander, Lauren Guckert
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Patent number: 9921808Abstract: Memristor-based adders using memristors-as-drivers (MAD) gates. As a result of employing MAD gates in memristor-based adders, such as ripple carry adders, carry select adders, conditional sum adders and carry lookahead adders, the number of delay steps may be less than half than the number of delay steps required in traditional CMOS implementations of adders. Furthermore, by using MAD gates, memristor-based adders can be implemented with less complexity (e.g., fewer memristors and drivers). As a result, by the memristor-based adders using MAD gates, the speed and complexity of a wide variety of arithmetic operations is improved.Type: GrantFiled: June 2, 2017Date of Patent: March 20, 2018Assignee: Board of Regents, The University of Texas SystemInventors: Earl Swartzlander, Lauren Guckert
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Patent number: 8166091Abstract: In an embodiment, a dot-product unit to perform single-precision floating-point product and addition operations is disclosed that includes a first multiplier tree unit adapted to multiply first and second significand operands to produce a first set of two partial products. The dot-product unit further includes a second multiplier tree unit adapted to multiply third and fourth significand operands to produce a second set of two partial products, a shared exponent compare unit adapted to compare exponents of the first, second, third and fourth operands to produce an alignment shift value, and an alignment unit adapted to shift the second set of two partial products based on the alignment shift value. The dot-product unit also includes an adder unit adapted to add or subtract the first set of two partial products and the second shifted set of two partial products to produce a dot-product value that is a single-precision floating-point value.Type: GrantFiled: November 10, 2008Date of Patent: April 24, 2012Assignee: Crossfield Technology LLCInventors: Earl Swartzlander, Jr., Hani Saleh
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Patent number: 8161090Abstract: In a particular embodiment, a method is disclosed that includes receiving first and second operands at a floating-point fused add-subtract circuit. The method further includes simultaneously performing add and subtract operations on the first and second operands via the floating-point fused add-subtract circuit to produce a sum result output and a difference result output. The floating-point fused add-subtract circuit includes sign logic, exponent adjustment logic, and shift logic that are shared by an add/round and post-normalize circuit and a subtract/round and post-normalize circuit to produce the sum and difference result outputs.Type: GrantFiled: December 5, 2008Date of Patent: April 17, 2012Assignee: Crossfield Technology LLCInventors: Earl Swartzlander, Jr., Jordan Hani Saleh
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Publication number: 20070214204Abstract: The present invention provides a solution to the shortcomings of the traditional two's complement system that is commonly utilized in modern computing systems and digital signal processors. The previously described shortcoming of the two's complement system are corrected in the present invention is a number system described as the negative two's complement system. In the negative two's complement system a n-bit number, A, has a sign bit, an-1, and n?1 fractional bits, an-2, an-3, . . . , a0. The value of an n-bit fractional negative two's complement number is: A = a n - 1 + ? i = 0 n - 2 ? - a i ? 2 i - n + 1 .Type: ApplicationFiled: March 8, 2006Publication date: September 13, 2007Inventor: Earl Swartzlander
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Publication number: 20070132490Abstract: A method and apparatus for capacitance multiplication using two charge pumps. A first charge pump (206) provides a current signal (1216) that is first conducted by a resistor (310) of an RC network and then split into three current paths prior to being conducted by a capacitor of the RC network. A first current path provides current to the capacitor (306) of the RC network from node (320). A second current path multiplies the current conducted by capacitor (306) by a first current multiplication factor. A third current path provides current to a second charge pump, which multiplies the current from the first charge pump by a second current multiplication factor that has a fractional value with an inverse magnitude sign relative to the first current multiplication factor. The combination of the second and third current paths effectively multiplies the capacitance magnitude of capacitor (306).Type: ApplicationFiled: December 12, 2005Publication date: June 14, 2007Applicant: Xilinx, Inc.Inventors: Moises Robinson, Marwan Hassoun, Earl Swartzlander
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Publication number: 20050160127Abstract: A modular pipeline algorithm and architecture for computing discrete Fourier transforms is described. For an N point transform, two pipeline N point {square root}{square root over (N)} point fast Fourier transform modules are combined with a center element. The center element contains memories, multipliers and control logic. Compared with standard N point pipeline FFT, the modular pipeline FFT maintains the bandwidth existing pipeline FFTs with reduced dynamic power consumption and reduced complexity of the overall hardware pipeline.Type: ApplicationFiled: November 2, 2004Publication date: July 21, 2005Inventors: Earl Swartzlander, Ayman Moustafa El-Khashab