Abstract: Memristor-based dividers using memristors-as-drivers (MAD) gates. As a result of employing MAD gates in memristor-based dividers, such as binary non-restoring dividers and SRT dividers, the number of delay steps may be less than half than the number of delay steps required in traditional CMOS implementations of dividers. Furthermore, by using MAD gates, memristor-based dividers can be implemented with less complexity (e.g., fewer memristors and drivers). As a result, by the memristor-based dividers using MAD gates, the speed and complexity of a wide variety of arithmetic operations is improved.

Abstract: Memristor-based multipliers using memristors-as-drivers (MAD) gates. As a result of employing MAD gates in memristor-based multipliers, such as shift-and-add multipliers, Booth multipliers and array multipliers, the number of delay steps may be less than half than the number of delay steps required in traditional CMOS implementations of multipliers. Furthermore, by using MAD gates, memristor-based multipliers can be implemented with less complexity (e.g., fewer memristors and drivers). As a result, by the memristor-based multipliers using MAD gates, the speed and complexity of a wide variety of arithmetic operations is improved.

Abstract: Memristor-based dividers using memristors-as-drivers (MAD) gates. As a result of employing MAD gates in memristor-based dividers, such as binary non-restoring dividers and SRT dividers, the number of delay steps may be less than half than the number of delay steps required in traditional CMOS implementations of dividers. Furthermore, by using MAD gates, memristor-based dividers can be implemented with less complexity (e.g., fewer memristors and drivers). As a result, by the memristor-based dividers using MAD gates, the speed and complexity of a wide variety of arithmetic operations is improved.

Abstract: Memristor-based dividers using memristors-as-drivers (MAD) gates. As a result of employing MAD gates in memristor-based dividers, such as binary non-restoring dividers and SRT dividers, the number of delay steps may be less than half than the number of delay steps required in traditional CMOS implementations of dividers. Furthermore, by using MAD gates, memristor-based dividers can be implemented with less complexity (e.g., fewer memristors and drivers). As a result, by the memristor-based dividers using MAD gates, the speed and complexity of a wide variety of arithmetic operations is improved.

Abstract: Memristor-based multipliers using memristors-as-drivers (MAD) gates. As a result of employing MAD gates in memristor-based multipliers, such as shift-and-add multipliers, Booth multipliers and array multipliers, the number of delay steps may be less than half than the number of delay steps required in traditional CMOS implementations of multipliers. Furthermore, by using MAD gates, memristor-based multipliers can be implemented with less complexity (e.g., fewer memristors and drivers). As a result, by the memristor-based multipliers using MAD gates, the speed and complexity of a wide variety of arithmetic operations is improved.

Abstract: Memristor-based dividers using memristors-as-drivers (MAD) gates. As a result of employing MAD gates in memristor-based dividers, such as binary non-restoring dividers and SRT dividers, the number of delay steps may be less than half than the number of delay steps required in traditional CMOS implementations of dividers. Furthermore, by using MAD gates, memristor-based dividers can be implemented with less complexity (e.g., fewer memristors and drivers). As a result, by the memristor-based dividers using MAD gates, the speed and complexity of a wide variety of arithmetic operations is improved.

Abstract: Memristor-based multipliers using memristors-as-drivers (MAD) gates. As a result of employing MAD gates in memristor-based multipliers, such as shift-and-add multipliers, Booth multipliers and array multipliers, the number of delay steps may be less than half than the number of delay steps required in traditional CMOS implementations of multipliers. Furthermore, by using MAD gates, memristor-based multipliers can be implemented with less complexity (e.g., fewer memristors and drivers). As a result, by the memristor-based multipliers using MAD gates, the speed and complexity of a wide variety of arithmetic operations is improved.

Abstract: Memristor-based dividers using memristors-as-drivers (MAD) gates. As a result of employing MAD gates in memristor-based dividers, such as binary non-restoring dividers and SRT dividers, the number of delay steps may be less than half than the number of delay steps required in traditional CMOS implementations of dividers. Furthermore, by using MAD gates, memristor-based dividers can be implemented with less complexity (e.g., fewer memristors and drivers). As a result, by the memristor-based dividers using MAD gates, the speed and complexity of a wide variety of arithmetic operations is improved.

Abstract: Memristor-based dividers using memristors-as-drivers (MAD) gates. As a result of employing MAD gates in memristor-based dividers, such as binary non-restoring dividers and SRT dividers, the number of delay steps may be less than half than the number of delay steps required in traditional CMOS implementations of dividers. Furthermore, by using MAD gates, memristor-based dividers can be implemented with less complexity (e.g., fewer memristors and drivers). As a result, by the memristor-based dividers using MAD gates, the speed and complexity of a wide variety of arithmetic operations is improved.

Abstract: Memristor-based multipliers using memristors-as-drivers (MAD) gates. As a result of employing MAD gates in memristor-based multipliers, such as shift-and-add multipliers, Booth multipliers and array multipliers, the number of delay steps may be less than half than the number of delay steps required in traditional CMOS implementations of multipliers. Furthermore, by using MAD gates, memristor-based multipliers can be implemented with less complexity (e.g., fewer memristors and drivers). As a result, by the memristor-based multipliers using MAD gates, the speed and complexity of a wide variety of arithmetic operations is improved.

Abstract: A new lower-power gate design for memristor-based Boolean operations. Such a design offers a uniform cell that is configurable to perform all Boolean operations, including the XOR operation. For example, a circuit to perform the AND operation utilizes a first memristor and a second memristor connected in series. The circuit further includes a switch, where a node of the second memristor is connected to the switch. Furthermore, the circuit includes a third memristor connected to the switch in series, where the switch and the third memristor are connected in parallel to the first and second memristors. Additionally, the first voltage source is connected to the first memristor via a first resistor. In addition, a second voltage source is connected in series to the switch and the third memristor. In such a design, the delay is reduced to a single step and the area is reduced to at most 3 memristors.

Abstract: A new lower-power gate design for memristor-based Boolean operations. Such a design offers a uniform cell that is configurable to perform all Boolean operations, including the XOR operation. For example, a circuit to perform the AND operation utilizes a first memristor and a second memristor connected in series. The circuit further includes a switch, where a node of the second memristor is connected to the switch. Furthermore, the circuit includes a third memristor connected to the switch in series, where the switch and the third memristor are connected in parallel to the first and second memristors. Additionally, the first voltage source is connected to the first memristor via a first resistor. In addition, a second voltage source is connected in series to the switch and the third memristor. In such a design, the delay is reduced to a single step and the area is reduced to at most 3 memristors.

Abstract: Memristor-based adders using memristors-as-drivers (MAD) gates. As a result of employing MAD gates in memristor-based adders, such as ripple carry adders, carry select adders, conditional sum adders and carry lookahead adders, the number of delay steps may be less than half than the number of delay steps required in traditional CMOS implementations of adders. Furthermore, by using MAD gates, memristor-based adders can be implemented with less complexity (e.g., fewer memristors and drivers). As a result, by the memristor-based adders using MAD gates, the speed and complexity of a wide variety of arithmetic operations is improved.

Abstract: Memristor-based adders using memristors-as-drivers (MAD) gates. As a result of employing MAD gates in memristor-based adders, such as ripple carry adders, carry select adders, conditional sum adders and carry lookahead adders, the number of delay steps may be less than half than the number of delay steps required in traditional CMOS implementations of adders. Furthermore, by using MAD gates, memristor-based adders can be implemented with less complexity (e.g., fewer memristors and drivers). As a result, by the memristor-based adders using MAD gates, the speed and complexity of a wide variety of arithmetic operations is improved.

Abstract: The present invention provides a solution to the shortcomings of the traditional two's complement system that is commonly utilized in modern computing systems and digital signal processors. The previously described shortcoming of the two's complement system are corrected in the present invention is a number system described as the negative two's complement system. In the negative two's complement system a n-bit number, A, has a sign bit, an-1, and n?1 fractional bits, an-2, an-3, . . . , a0. The value of an n-bit fractional negative two's complement number is: A = a n - 1 + ? i = 0 n - 2 ? - a i ? 2 i - n + 1 .

Abstract: A method and apparatus for capacitance multiplication using two charge pumps. A first charge pump (206) provides a current signal (1216) that is first conducted by a resistor (310) of an RC network and then split into three current paths prior to being conducted by a capacitor of the RC network. A first current path provides current to the capacitor (306) of the RC network from node (320). A second current path multiplies the current conducted by capacitor (306) by a first current multiplication factor. A third current path provides current to a second charge pump, which multiplies the current from the first charge pump by a second current multiplication factor that has a fractional value with an inverse magnitude sign relative to the first current multiplication factor. The combination of the second and third current paths effectively multiplies the capacitance magnitude of capacitor (306).

Abstract: A modular pipeline algorithm and architecture for computing discrete Fourier transforms is described. For an N point transform, two pipeline N point {square root}{square root over (N)} point fast Fourier transform modules are combined with a center element. The center element contains memories, multipliers and control logic. Compared with standard N point pipeline FFT, the modular pipeline FFT maintains the bandwidth existing pipeline FFTs with reduced dynamic power consumption and reduced complexity of the overall hardware pipeline.