Patents by Inventor Earl Swartzlander, Jr.

Earl Swartzlander, Jr. has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8166091
    Abstract: In an embodiment, a dot-product unit to perform single-precision floating-point product and addition operations is disclosed that includes a first multiplier tree unit adapted to multiply first and second significand operands to produce a first set of two partial products. The dot-product unit further includes a second multiplier tree unit adapted to multiply third and fourth significand operands to produce a second set of two partial products, a shared exponent compare unit adapted to compare exponents of the first, second, third and fourth operands to produce an alignment shift value, and an alignment unit adapted to shift the second set of two partial products based on the alignment shift value. The dot-product unit also includes an adder unit adapted to add or subtract the first set of two partial products and the second shifted set of two partial products to produce a dot-product value that is a single-precision floating-point value.
    Type: Grant
    Filed: November 10, 2008
    Date of Patent: April 24, 2012
    Assignee: Crossfield Technology LLC
    Inventors: Earl Swartzlander, Jr., Hani Saleh
  • Patent number: 8161090
    Abstract: In a particular embodiment, a method is disclosed that includes receiving first and second operands at a floating-point fused add-subtract circuit. The method further includes simultaneously performing add and subtract operations on the first and second operands via the floating-point fused add-subtract circuit to produce a sum result output and a difference result output. The floating-point fused add-subtract circuit includes sign logic, exponent adjustment logic, and shift logic that are shared by an add/round and post-normalize circuit and a subtract/round and post-normalize circuit to produce the sum and difference result outputs.
    Type: Grant
    Filed: December 5, 2008
    Date of Patent: April 17, 2012
    Assignee: Crossfield Technology LLC
    Inventors: Earl Swartzlander, Jr., Jordan Hani Saleh