Abstract: A data processing system having a first logical device capable of sending and receiving clocked electronic data and a second logical device connected to the first logical device, the second logical device also being capable of sending and receiving clocked electronic data. A controller is connected to the first and second logical devices for controlling data transfer therebetween. The controller includes a clock edge generator and gating logic connected thereto for allowing the first logical device to accept data and the second logical device to send data during a time interval of an odd number of clock edges.

Abstract: In a multiprocessor system, including a first processor, a second processor, a main memory (otherwise termed a Basic Storage Module - BSM), and a control circuit (termed BSM controls), the first processor may attempt to locate specific data in its cache and fail to locate this data. The first processor will query the cache of the second processor in an attempt to locate the specific data. If the data is located, an indication of the existence of the data in the cache of the second processor is sent and stored in a status register associated with the second processor. As a result, preliminary steps have been taken to "flush" or move the data from the cache of the second processor to the BSM in order for the first processor to utilize the data. However, prior to the flush operation, it is necessary for the second processor to synchronize its clocks with the clocks of the BSM controls. When this synchronization is complete, the data in the cache of the second processor is flushed or moved to the BSM.

Abstract: A masking circuit for a multiprocessor system is disclosed. The masking circuit senses the existence and type of commands stored in the command status registers associated with the system processors. Masking begins if it is determined that information needed by one processor is located in the cache memory of another processor and is to be flushed to the main memory, which is accessible by the first processor. The masking circuit masks the command present in the command status register associated with the first processor, for the first processor to access the main memory, until after the information has been flushed from the cache to the main memory. The first processor is thus prevented from accessing the main memory until after the information has been flushed thereto.