Abstract: There is disclosed a frequency monitor circuit, for monitoring AC power frequency for example, in which a gate is provided for a stable oscillator and frequency divider circuit which is responsive to the frequency divided monitored signal and a flip-flop circuit to produce a fixed reference period signal equal to a predetermined number of cycles of the oscillator commencing at the beginning of a full cycle of the monitored signal; a two-stage timer which determines the tolerance for the monitored signal frequency and is adjustable is provided with signals from the monitored signal divider circuit and the fixed reference period circuit and arranged so that the end of the reference period or the end of the divided monitored signal cycle, whichever occurs first, will start the timer. Its output latches a pair of flip-flop circuits acting as decoders which are respectively supplied with the state of the frequency divided monitored signal and the fixed reference period signal.

Abstract: There is disclosed an electro-mechanical sequencer to equalize the running time of multiple (typically four) pumps in a common sump at a sewage treatment plant or the like. The sequencer includes a solid state binary counter receiving an input at an all-pumps-off condition. The binary counter operates a pair of multi-pole-double-throw relays. Control signals (typically four) from float valves or other sensing devices to the pump motors are routed through the first relay and then the second relay; one of the relays shifts the connection of its inputs and outputs by one position; the other relay shifts by two positions. Upon successive input signals to the binary counter the relays are changed from no-shift, to one position shift, two position shift, three position shift, and back to no-shift (in four pump systems). Three pump systems return to no-shift after the two position shift.