Patents by Inventor Earle F. Philhower, III
Earle F. Philhower, III has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8719465Abstract: A distributed direct memory access (DMA) method, apparatus, and system is provided within a system on chip (SOC). DMA controller units are distributed to various functional modules desiring direct memory access. The functional modules interface to a systems bus over which the direct memory access occurs. A global buffer memory, to which the direct memory access is desired, is coupled to the system bus. Bus arbitrators are utilized to arbitrate which functional modules have access to the system bus to perform the direct memory access. Once a functional module is selected by the bus arbitrator to have access to the system bus, it can establish a DMA routine with the global buffer memory.Type: GrantFiled: January 30, 2013Date of Patent: May 6, 2014Assignee: Intel CorporationInventors: Kumar Ganapathy, Ruban Kanapathippillai, Saurin Shah, George Moussa, Earle F. Philhower, III, Ruchir Shah
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Publication number: 20130138877Abstract: A distributed direct memory access (DMA) method, apparatus, and system is provided within a system on chip (SOC). DMA controller units are distributed to various functional modules desiring direct memory access. The functional modules interface to a systems bus over which the direct memory access occurs. A global buffer memory, to which the direct memory access is desired, is coupled to the system bus. Bus arbitrators are utilized to arbitrate which functional modules have access to the system bus to perform the direct memory access. Once a functional module is selected by the bus arbitrator to have access to the system bus, it can establish a DMA routine with the global buffer memory.Type: ApplicationFiled: January 30, 2013Publication date: May 30, 2013Inventors: Kumar Ganapathy, Ruban Kanapathippillai, Saurin Shah, George Moussa, Earle F. Philhower, III, Ruchir Shah
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Patent number: 8386665Abstract: A distributed direct memory access (DMA) method, apparatus, and system is provided within a system on chip (SOC). DMA controller units are distributed to various functional modules desiring direct memory access. The functional modules interface to a systems bus over which the direct memory access occurs. A global buffer memory, to which the direct memory access is desired, is coupled to the system bus. Bus arbitrators are utilized to arbitrate which functional modules have access to the system bus to perform the direct memory access. Once a functional module is selected by the bus arbitrator to have access to the system bus, it can establish a DMA routine with the global buffer memory.Type: GrantFiled: June 28, 2011Date of Patent: February 26, 2013Assignee: Intel CorporationInventors: Kumar Ganapathy, Ruban Kanapathippillai, Saurin Shah, George Moussa, Earle F. Philhower, III, Ruchir Shah
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Publication number: 20110320672Abstract: A distributed direct memory access (DMA) method, apparatus, and system is provided within a system on chip (SOC). DMA controller units are distributed to various functional modules desiring direct memory access. The functional modules interface to a systems bus over which the direct memory access occurs. A global buffer memory, to which the direct memory access is desired, is coupled to the system bus. Bus arbitrators are utilized to arbitrate which functional modules have access to the system bus to perform the direct memory access. Once a functional module is selected by the bus arbitrator to have access to the system bus, it can establish a DMA routine with the global buffer memory.Type: ApplicationFiled: June 28, 2011Publication date: December 29, 2011Inventors: Kumar Ganapathy, Ruban Kanapathippillai, Saurin Shah, George Moussa, Earle F. Philhower, III, Ruchir Shah
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Patent number: 7970961Abstract: A distributed direct memory access (DMA) method, apparatus, and system is provided within a system on chip (SOC). DMA controller units are distributed to various functional modules desiring direct memory access. The functional modules interface to a systems bus over which the direct memory access occurs. A global buffer memory, to which the direct memory access is desired, is coupled to the system bus. Bus arbitrators are utilized to arbitrate which functional modules have access to the system bus to perform the direct memory access. Once a functional module is selected by the bus arbitrator to have access to the system bus, it can establish a DMA routine with the global buffer memory.Type: GrantFiled: November 11, 2008Date of Patent: June 28, 2011Assignee: Intel CorporationInventors: Kumar Ganapathy, Ruban Kanapathippillai, Saurin Shah, George Moussa, Earle F. Philhower, III, Ruchir Shah
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Publication number: 20090070513Abstract: A distributed direct memory access (DMA) method, apparatus, and system is provided within a system on chip (SOC). DMA controller units are distributed to various functional modules desiring direct memory access. The functional modules interface to a systems bus over which the direct memory access occurs. A global buffer memory, to which the direct memory access is desired, is coupled to the system bus. Bus arbitrators are utilized to arbitrate which functional modules have access to the system bus to perform the direct memory access. Once a functional module is selected by the bus arbitrator to have access to the system bus, it can establish a DMA routine with the global buffer memory.Type: ApplicationFiled: November 11, 2008Publication date: March 12, 2009Inventors: Kumar Ganapathy, Ruban Kanapathippillai, Saurin Shah, George Moussa, Earle F. Philhower, III, Ruchir Shah
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Patent number: 7502977Abstract: A reconfigurable memory in an integrated circuit includes an array of memory cells and a memory controller. The array of memory cells in the reconfigurable memory are tested to determine if they are unusable and if so, their associated physical addresses corresponding to their physical location. After determining the physical addresses where any failure exists, the physical addresses locations associated with the physical locations of unusable memory cells or memory blocks are mapped out to avoid addressing them. While mapping out unusable memory locations or memory blocks reduces the total capacity, the reconfigurable memory has sufficient capacity for the integrated circuit to remain functionally usable.Type: GrantFiled: January 21, 2005Date of Patent: March 10, 2009Assignee: Intel CorporationInventors: Siva Venkatraman, Earle F. Philhower, III, Ruban Kanapathippillai, Manoj Mehta
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Patent number: 7490260Abstract: A reconfigurable memory in an integrated circuit includes an array of memory cells and a memory controller. The array of memory cells in the reconfigurable memory are tested to determine if they are unusable and if so, their associated physical addresses corresponding to their physical location. After determining the physical addresses where any failure exists, the physical addresses locations associated with the physical locations of unusable memory cells or memory blocks are mapped out to avoid addressing them. While mapping out unusable memory locations or memory blocks reduces the total capacity, the reconfigurable memory has sufficient capacity for the integrated circuit to remain functionally usable.Type: GrantFiled: September 1, 2005Date of Patent: February 10, 2009Assignee: Intel CorporationInventors: Siva Venkatraman, Earle F. Philhower, III, Ruban Kanapathippillai, Manoj Mehta
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Patent number: 7464197Abstract: A distributed direct memory access (DMA) method, apparatus, and system is provided within a system on chip (SOC). DMA controller units are distributed to various functional modules desiring direct memory access. The functional modules interface to a systems bus over which the direct memory access occurs. A global buffer memory, to which the direct memory access is desired, is coupled to the system bus. Bus arbitrators are utilized to arbitrate which functional modules have access to the system bus to perform the direct memory access. Once a functional module is selected by the bus arbitrator to have access to the system bus, it can establish a DMA routine with the global buffer memory.Type: GrantFiled: January 14, 2005Date of Patent: December 9, 2008Assignee: Intel CorporationInventors: Kumar Ganapathy, Ruban Kanapathippillai, Saurin Shah, George Moussa, Earle F. Philhower, III, Ruchir Shah
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Patent number: 7318115Abstract: Method and apparatus for reducing power consumption in a digital specific signal processor integrated circuit. Data buses are routed through multiplexers to reduce the number of busses routed across an integrated circuit and maintain their prior state. Global memory is clustered into memory clusters. The memory cluster having a memory block to be accessed is activated without activating other memory clusters in the global memory. Inactive data buses retain their state by use of bus state keepers. A loop buffer stores instructions within program loops to avoid memory accesses. Functional blocks can have their clocks gated instruction by instruction to lower power consumption. RISC and DSP units swap circuit activity to reduce power consumption. Local data memory is includes self-timed memory access activation and provides for off boundary access to further lower power consumption.Type: GrantFiled: August 27, 2003Date of Patent: January 8, 2008Assignee: Intel CorporationInventors: Ruban Kanapathippillai, Kumar Ganapathy, Thu Nguyen, Siva Venkatraman, Earle F. Philhower, III, Manoj Mehta, Kenneth Malich
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Patent number: 7287148Abstract: An integrated circuit comprising a reduced instruction set computer (RISC) controller to execute RISC instructions, one or more digital signal processing (DSP) units to execute DSP instructions, and a unified instruction pipeline coupled to the RISC controller and the one or more DSP units, the unified instruction pipeline to decode and initiate execution of the RISC instructions and the DSP instructions of a unified RISC and DSP instruction set, the unified instruction pipeline to decode and initiate the RISC instructions when the DSP instructions are inactive, and to decode and initiate the DSP instructions when the RISC instructions are inactive.Type: GrantFiled: August 28, 2003Date of Patent: October 23, 2007Assignee: Intel CorporationInventors: Ruban Kanapathippillai, Kumar Ganapathy, Thu Nguyen, Siva Venkatraman, Earle F. Philhower, III, Manoj Mehta, Kenneth Malich
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Patent number: 7233166Abstract: Bus state keepers to maintain a steady state of an inactive bus to conserve power. In one embodiment of the invention, the bus state keepers include a plurality of multiplexers and a plurality of flip flops. The plurality of flip flops to store a state of a bus in response to a select signal.Type: GrantFiled: August 27, 2003Date of Patent: June 19, 2007Assignee: Intel CorporationInventors: Ruban Kanapathippillai, Kumar Ganapathy, Thu Nguyen, Siva Venkatraman, Earle F. Philhower, III, Manoj Mehta, Kenneth Malich
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Patent number: 7155541Abstract: A direct memory access (DMA) descriptor table to control DMA of information in a memory is disclosed. The DMA descriptor table includes one or more DMA descriptor lists stored in the memory. Each DMA descriptor lists may include one or more pointers and information regarding the type of data being directly memory accessed. The pointers may point to a starting address in the memory from which to directly memory access data, prior state information, or program code from and to the memory.Type: GrantFiled: January 14, 2005Date of Patent: December 26, 2006Assignee: Intel CorporationInventors: Kumar Ganapathy, Ruban Kanapathippillai, Saurin Shah, George Moussa, Earle F. Philhower, III, Ruchir Shah
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Patent number: 7111190Abstract: A reconfigurable memory in an integrated circuit includes an array of memory cells and a memory controller. The array of memory cells in the reconfigurable memory are tested to determine if they are unusable and if so, their associated physical addresses corresponding to their physical location. After determining the physical addresses where any failure exists, the physical addresses locations associated with the physical locations of unusable memory cells or memory blocks are mapped out to avoid addressing them. While mapping out unusable memory locations or memory blocks reduces the total capacity, the reconfigurable memory has sufficient capacity for the integrated circuit to remain functionally usable.Type: GrantFiled: January 24, 2002Date of Patent: September 19, 2006Assignee: Intel CorporationInventors: Siva Venkatraman, Earle F. Philhower, III, Ruban Kanapathippillai, Manoj Mehta
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Patent number: 6874039Abstract: A distributed direct memory access (DMA) method, apparatus, and system is provided within a system on chip (SOC). DMA controller units are distributed to various functional modules desiring direct memory access. The functional modules interface to a systems bus over which the direct memory access occurs. A global buffer memory, to which the direct memory access is desired, is coupled to the system bus. Bus arbitrators are utilized to arbitrate which functional modules have access to the system bus to perform the direct memory access. Once a functional module is selected by the bus arbitrator to have access to the system bus, it can establish a DMA routine with the global buffer memory.Type: GrantFiled: September 7, 2001Date of Patent: March 29, 2005Assignee: Intel CorporationInventors: Kumar Ganapathy, Ruban Kanapathippillai, Saurin Shah, George Moussa, Earle F. Philhower, III, Ruchir Shah
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Patent number: 6732203Abstract: In one embodiment, a bus multiplexer is between a memory and a functional unit of the integrated circuit. An input of the bus multiplexer couples to a global bus having a bit width. A local bus having a lesser bit width couples to an output of the bus multiplexer. The bus multiplexer selectively multiplexes bits of data on the global bus onto bits of the local bus. In another embodiment, an integrated circuit comprises a memory, a global bus, and a functional unit coupled together. The functional unit includes a bus multiplexer with an input coupled to the global bus, and a local bus coupled to an output of the bus multiplexer. The bus width of the local bus is less than that of the global bus. The bus multiplexer selects data from a subset of bits of the global bus to couple onto the bits of the local bus.Type: GrantFiled: March 29, 2002Date of Patent: May 4, 2004Assignee: Intel CorporationInventors: Ruban Kanapathippillai, Kumar Ganapathy, Thu Nguyen, Siva Venkatraman, Earle F. Philhower, III, Manoj Mehta, Kenneth Malich