Abstract: A circuit is provided which contains memory, logic, arithmetic and control circuitry needed to generate all or part of a frame for use in video processing and animation as well as digital signal and image processing. One or more such circuits are provided on an integrated circuit. A video or image frame generation system is constructed from one or more of these integrated circuits, optionally with additional memory circuitry, to provide exceptional performance in frame production for animation, particularly 3-D and other high performance applications such as medical imaging, virtual reality and real-time scene generation in video games and simulation environments. The circuit(s) are used to process high speed object-oriented graphics related streams such as proposed by MPEG 4, as well as act as a single chip JAVA engine with highly optimized numeric performance.

Abstract: An arithmetic circuit for calculating floating point operations. The circuit comprises first and second blocks of consecutive logic cells. Each logic block has a first cell and a last cell, with the first cell through the next to last cell having an output that is coupled to the next adjacent cell. The coupling of the last cells of the first and second logic blocks depends on the value of a control signal. A comparator may be used to generate the control signal.

Abstract: A multi-port packet processor on an integrated circuit provides an efficient means to interface multiple high-speed packet-based communications channels. The multi-port packet processor includes multiple port processors. Each port processor can include a channel interface for coupling to a respective communications channel, a channel processor for processing the data packets received through the channel interface, and an interprocessor communications interface for providing communication between the port processors. The channel interface can be designed to process data packets using a particular set of packet-based protocols. Alternatively, the channel interface can be designed having programmable controls to allow processing of data packets using a selected set, from a number of possible sets, of packet-based protocols.

Abstract: A device for performing single precision floating point arithmetic. The device includes a shared operand generator that receives an operand and outputs a result that is a fixed function of the operand. It also includes an arithmetic circuit comprising a plurality of multiply circuits that calculate partial products of a first and second operand and the result of the shared operand generator. It also includes circuitry to calculate the sum of the partial products and a third operand to produce the arithmetic result.

Abstract: Computer systems may be provided with additional performance for demanding applications while adding little additional hardware. For example, a slave device for a host computer system combines an embedded programmable controller with non-volatile memory, local RAM, and interface logic. The host computer system treats the slave device as if it would be a hierarchical memory system such as a conventional disk drive on which it may store and retrieve files. Additionally, the host computer system may program the controller to perform operations on stored information, including image processing and/or data compression. The non-volatile memory may include a disk drive, writable CD-ROM, optical drive, or non-volatile solid state memory.

Abstract: A programmable logic device (PLD) and configurable logic network in which one or more logic combination networks (LCN) each receives logic inputs from two or more PLDs (PLD1, PLD2) and generates logic outputs (O, P) which provide inputs to programmable selectors (POR, UCL, . . . ) for controlling implementation of logic functions of various types and functionality by a controllable logic function sub-network by routing through the sub-network, logic values and logic instructions originating externally of the PLD's. Each programmable logic device includes an AND logic array (FAND . . . ) having inputs for receiving signals (Ax, Bx) and generating product term output signals and an OR logic array (OG . . . ) having inputs for receiving signals and generating sum term output signals (OF . . . ).

Abstract: A programmable logic device includes groups of AND logic function gates, the AND logic function gates in each group coupled to a logic OR function output gate associated with that AND logic function gate group. Each AND logic function gate group includes an output AND logic function gate having inputs that are programmable by respective programmable logic function generators (PLFG) of a set of PLFGs operatively associated with that output AND logic function gate. The PLFGs in any set of PLFGs receive the same sets of first logic input groups, and second programmable inputs. Operation of Boolean function generator output stages to carry out logic operations is controlled by first inputs from the logic OR function gates, and second programmable inputs received from logic cells according to logic inputs to said programmable cells. Inputs from the logic OR function gates are selected by programmable OR logic function generators.

Abstract: A logic system comprising one or more logic networks that can perform a variety of preconfigured or preconfiguarable logic functions. Each logic network is functionally separate from but operatively associated with one or more programmable circuits from which the logic network receives various logic signals. A first logic signal selects or preconfigures the desired logic function to be performed by the or each logic network while a second logic signal controls the operation of the selected logical function. The first logic signal can select a particular logic function to be performed by the logic network based on the contents of programmable cells in the network that are separate from the programmable circuits that supply the logic signals. Alternatively, the first logic signals can switch between various sub-networks each dedicated to performance of a preconfigured logic function.

Abstract: In the present invention, a reprogrammable control circuit is disclosed. The reprogrammable control circuit comprises a single-bit register for serially receiving an input bit signal and providing a control signal. The control signal represents the state of the bit stored in the register. A transmission gate means receives the control signal from the single-bit shift register and an input signal and provides an output signal therefrom. The control signal of the bit shift register is used to control the transmission of the input signal to the output signal. A plurality of reprogrammable control circuit which comprises a plurality of bit shift registers, each having a transmission gate means associated therewith is also disclosed. The reprogrammable control circuit can be used in an improved PLA, improved RAM, improved RCIM, improved ALU, improved counter, improved CAM, PCN to improve the reliability of routing signals and power, and to preserve the states of flip-flops.