Patents by Inventor Ebbin Raney SOUTHERLAND, JR.

Ebbin Raney SOUTHERLAND, JR. has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and apparatus for generating three-dimensional integrated circuit design
    Patent number: 11625522
    Abstract: A method and apparatus for generating a design for a 3D integrated circuit (3DIC) comprises extracting at least one design characteristic from a first data representation of a design for a 2D integrated circuit (2DIC) generated according to the design criteria required for the 3DIC. Components of the 3DIC are partitioned into groups (each representing one tier of the 3DIC) based on the extracted design characteristic. A second data representation of a 2DIC design is generated comprising multiple adjacent partitions each comprising the component groups for one tier of the 3DIC design together with inter-tier via ports representing locations of inter-tier vias. A placement for each partition is determined separately from a placement of corresponding components of the 2DIC represented by the original first data representation. This approach allows a 2DIC EDA tool to be used for designing a 3DIC.
    Type: Grant
    Filed: April 29, 2020
    Date of Patent: April 11, 2023
    Assignee: Arm Limited
    Inventors: Saurabh Pijuskumar Sinha, Kyungwook Chang, Brian Tracy Cline, Ebbin Raney Southerland, Jr.
  • METHOD AND APPARATUS FOR GENERATING THREE-DIMENSIONAL INTEGRATED CIRCUIT DESIGN
    Publication number: 20200257841
    Abstract: A method and apparatus for generating a design for a 3D integrated circuit (3DIC) comprises extracting at least one design characteristic from a first data representation of a design for a 2D integrated circuit (2DIC) generated according to the design criteria required for the 3DIC. Components of the 3DIC are partitioned into groups (each representing one tier of the 3DIC) based on the extracted design characteristic. A second data representation of a 2DIC design is generated comprising multiple adjacent partitions each comprising the component groups for one tier of the 3DIC design together with inter-tier via ports representing locations of inter-tier vias. A placement for each partition is determined separately from a placement of corresponding components of the 2DIC represented by the original first data representation. This approach allows a 2DIC EDA tool to be used for designing a 3DIC.
    Type: Application
    Filed: April 29, 2020
    Publication date: August 13, 2020
    Inventors: Saurabh Pijuskumar SINHA, Kyungwook CHANG, Brian Tracy CLINE, Ebbin Raney SOUTHERLAND, JR.
  • Method for generating three-dimensional integrated circuit design
    Patent number: 10678985
    Abstract: A method for generating a design for a 3D integrated circuit (3DIC) comprises extracting at least one design characteristic from a first data representation of a design for a integrated circuit (2DIC) generated according to the design criteria required for the 3DIC. Components of the 3DIC are partitioned into groups (each representing one tier of the 3DIC) based on the extracted design characteristic. A second data representation of a 2DIC design is generated comprising multiple adjacent partitions each comprising the component groups for one tier of the 3DIC design together with inter-tier via ports representing locations of inter-tier vias. A placement for each partition is determined separately from a placement of corresponding components of the 2DIC represented by the original first data representation. This approach allows a 2DIC EDA tool to be used for designing a 3DIC.
    Type: Grant
    Filed: August 31, 2016
    Date of Patent: June 9, 2020
    Assignee: ARM Limited
    Inventors: Saurabh Pijuskumar Sinha, Kyungwook Chang, Brian Tracy Cline, Ebbin Raney Southerland, Jr.
  • METHOD FOR GENERATING THREE-DIMENSIONAL INTEGRATED CIRCUIT DESIGN
    Publication number: 20180060475
    Abstract: A method for generating a design for a 3D integrated circuit (3DIC) comprises extracting at least one design characteristic from a first data representation of a design for a integrated circuit (2DIC) generated according to the design criteria required for the 3DIC. Components of the 3DIC are partitioned into groups (each representing one tier of the 3DIC) based on the extracted design characteristic. A second data representation of a 2DIC design is generated comprising multiple adjacent partitions each comprising the component groups for one tier of the 3DIC design together with inter-tier via ports representing locations of inter-tier vias. A placement for each partition is determined separately from a placement of corresponding components of the 2DIC represented by the original first data representation. This approach allows a 2DIC EDA tool to be used for designing a 3DIC.
    Type: Application
    Filed: August 31, 2016
    Publication date: March 1, 2018
    Inventors: Saurabh Pijuskumar SINHA, Kyungwook CHANG, Brian Tracy CLINE, Ebbin Raney SOUTHERLAND, JR.