Patents by Inventor Eben Upton

Eben Upton has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150271504
    Abstract: Various methods and systems are provided for adaptable video architectures. In one embodiment, a method for adapting video processing of a video device includes processing a video stream along a first pipeline pathway defined by a plurality of interconnected pipeline elements. In response to detecting a change in a system condition of the video device, the pipeline pathway is transitioned to a second pipeline pathway by reconfiguring at least one of the pipeline element interconnections. In another embodiment, a method includes obtaining a video stream. A first subset bitstream having a first resolution is processed in a video pipeline of a video device and video information is extracted from the video pipeline during the processing. At least a portion of the extracted video information is then to a video pipeline of the video device for processing a second subset bitstream having a second resolution higher than the first resolution.
    Type: Application
    Filed: June 4, 2015
    Publication date: September 24, 2015
    Inventors: Eben UPTON, Graham VEITCH, Alan MORGAN, James BENNETT
  • Patent number: 9135036
    Abstract: Methods and systems for reducing communication during video processing utilizing merge buffering are disclosed and may include storing data in a merge buffer in the virtual machine layer in a wireless communication device comprising a virtual machine user layer, a native user layer, a kernel, and a video processor. The data may then be communicated to the kernel via the native user layer. The data may include function calls, and/or kernel remote procedure calls. The data may be communicated via an application programming interface. Video data may be processed in the video processor based on the communicated data. The virtual machine user layer may include a Java environment. The data may be communicated to the kernel via the native user layer when the merge buffer is full or filled to a predetermined level.
    Type: Grant
    Filed: January 13, 2010
    Date of Patent: September 15, 2015
    Assignee: Broadcom Corporation
    Inventor: Eben Upton
  • Patent number: 9083951
    Abstract: Various methods and systems are provided for adaptable video architectures. In one embodiment, a method for adapting video processing of a video device includes processing a video stream along a first pipeline pathway defined by a plurality of interconnected pipeline elements. In response to detecting a change in a system condition of the video device, the pipeline pathway is transitioned to a second pipeline pathway by reconfiguring at least one of the pipeline element interconnections. In another embodiment, a method includes obtaining a video stream. A first subset bitstream having a first resolution is processed in a video pipeline of a video device and video information is extracted from the video pipeline during the processing. At least a portion of the extracted video information is then to a video pipeline of the video device for processing a second subset bitstream having a second resolution higher than the first resolution.
    Type: Grant
    Filed: September 30, 2011
    Date of Patent: July 14, 2015
    Assignee: Broadcom Corporation
    Inventors: Eben Upton, Graham Veitch, Alan Morgan, James Bennett
  • Patent number: 9058685
    Abstract: A graphics processing device generates control lists for controlling processing of 3D graphics. Control lists comprise primitive data for the 3D graphics, pointers to primitive data and control data. Tags that correspond to records within the control lists may be utilized for the control of processing. The graphics processing device may comprise a 3D pipeline comprising parallel processors. Processing is performed on a tile by tile basis and comprises a tile binning phase and/or a tile rendering phase. The two phases of processing may be performed in parallel on different sets of data. Control lists comprise a main list and/or sub-lists, for example, tile lists. Control lists may comprise links to other lists. Processing control may advance through the control lists without interaction from a driver and/or from a processor that is external to the graphics processing device.
    Type: Grant
    Filed: November 9, 2010
    Date of Patent: June 16, 2015
    Assignee: Broadcom Corporation
    Inventors: Gary Keall, Giles Edkins, Eben Upton, James Adams
  • Patent number: 8854384
    Abstract: In a graphics processing device, a plurality of processors write fragment shading results for order-dependent data to a buffer, according to the order in which the data is received. Fragment shading results for order-neutral data is written to the buffer one batch at a time. The order-dependent data comprises spatially overlapping data. Order-neutral data may not overlap. A scheduler controls the order of reception of one batch of data at a time by the processors. The order for receiving the order-dependent data may be determined. The plurality of processors may process the data in parallel. A writing order for writing results to a buffer from the processing in parallel, may be enforced. A portion of the processors may be instructed to wait before writing results to the buffer in a specified order. Processors signal when writing results to the buffer is complete.
    Type: Grant
    Filed: November 24, 2010
    Date of Patent: October 7, 2014
    Assignee: Broadcom Corporation
    Inventors: Gary Keall, Giles Edkins, Eben Upton, James Adams
  • Patent number: 8832412
    Abstract: Various methods and systems are provided for processing units that may be scaled. In one embodiment, a processing unit includes a plurality of scalar processing units and a vector processing unit in communication with each of the plurality of scalar processing units. The vector processing unit is configured to coordinate execution of instructions received from the plurality of scalar processing units. In another embodiment, a scalar instruction packet including a pre-fix instruction and a vector instruction packet including a vector instruction is obtained. Execution of the vector instruction may be modified by the pre-fix instruction in a processing unit including a vector processing unit. In another embodiment, a scalar instruction packet including a plurality of partitions is obtained. The location of the partitions is determined based upon a partition indicator included in the scalar instruction packet and a scalar instruction included in a partition is executed by a processing unit.
    Type: Grant
    Filed: September 20, 2011
    Date of Patent: September 9, 2014
    Assignee: Broadcom Corporation
    Inventors: Neil Bailey, Eben Upton
  • Patent number: 8692848
    Abstract: A method and system are provided in which one or more processors and/or circuits are operable to generate position information for a plurality of primitives utilizing a coordinate shader, one or more lists based on the generated position information, and rendering information for the plurality of primitives utilizing a vertex shader and the generated one or more lists. The generated one or more lists may comprise indices associated with one or more primitives from the plurality of primitives and with one or more tiles from a plurality of tiles in a screen plane. The position information and the one or more lists may be generated during a first rendering phase, and the rendering information may be generated during a second rendering phase different from the first rendering phase. The coordinate shader may perform a subset of the operations supported by the vertex shader.
    Type: Grant
    Filed: August 25, 2010
    Date of Patent: April 8, 2014
    Assignee: Broadcom Corporation
    Inventors: James Adams, Gary Keall, Eben Upton, Giles Edkins
  • Patent number: 8619085
    Abstract: A graphics processing device may generate coordinates for vertices of graphics primitives in a view-space. Tiles are defined within the view-space and are associated with tile lists. Primitives and/or vertices which overlap a tile are determined. Tile lists comprise differentially encoded indices and/or spatial coordinates for overlapping primitives. The differential encoding may or may not be byte aligned. During tile mode graphics rendering, tile lists are utilized to reference vertex attributes and/or primitives. Graphics rendering comprises a tile binning phase and a tile rendering phase. The primitives may comprise a triangle and/or joined triangles that share one or more vertices. For multiple joined primitives, information about shared vertices may be encoded without repetition for each primitive. Coordinates and/or corresponding weights for new vertices are encoded in a tile list and utilized for interpolating properties of the new vertices based on attributes of the original vertices.
    Type: Grant
    Filed: November 23, 2010
    Date of Patent: December 31, 2013
    Assignee: Broadcom Corporation
    Inventors: Gary Keall, Giles Edkins, Eben Upton, James Adams
  • Patent number: 8505001
    Abstract: A method and system are provided in which one or more processors may be operable to generate an intermediate representation of a shader source code, wherein the intermediate representation comprises one or more whole-program data flow graph representations of the shader source code. The one or more processors may be operable to generate machine code based on the generated intermediate representation of the shader source code. The one or more whole-program data flow graph representations of the shader source code may be generated utilizing a compiler front end. The machine code may be generated utilizing a compiler back end. The generated machine code may be executable by a graphics processor. The generated machine code may be executable by a processor comprising a single-instruction multiple-data (SIMD) architecture. The generated machine code may be executable to perform coordinate and/or vertex shading of image primitives.
    Type: Grant
    Filed: August 25, 2010
    Date of Patent: August 6, 2013
    Assignee: Broadcom Corporation
    Inventor: Eben Upton
  • Publication number: 20130022101
    Abstract: Various methods and systems are provided for adaptable video architectures. In one embodiment, a method for adapting video processing of a video device includes processing a video stream along a first pipeline pathway defined by a plurality of interconnected pipeline elements. In response to detecting a change in a system condition of the video device, the pipeline pathway is transitioned to a second pipeline pathway by reconfiguring at least one of the pipeline element interconnections. In another embodiment, a method includes obtaining a video stream. A first subset bitstream having a first resolution is processed in a video pipeline of a video device and video information is extracted from the video pipeline during the processing. At least a portion of the extracted video information is then to a video pipeline of the video device for processing a second subset bitstream having a second resolution higher than the first resolution.
    Type: Application
    Filed: September 30, 2011
    Publication date: January 24, 2013
    Applicant: BROADCOM CORPORATION
    Inventors: Eben Upton, Graham Veitch, Alan Morgan, James Bennett
  • Publication number: 20130024652
    Abstract: Various methods and systems are provided for processing units that may be scaled. In one embodiment, a processing unit includes a plurality of scalar processing units and a vector processing unit in communication with each of the plurality of scalar processing units. The vector processing unit is configured to coordinate execution of instructions received from the plurality of scalar processing units. In another embodiment, a scalar instruction packet including a pre-fix instruction and a vector instruction packet including a vector instruction is obtained. Execution of the vector instruction may be modified by the pre-fix instruction in a processing unit including a vector processing unit. In another embodiment, a scalar instruction packet including a plurality of partitions is obtained. The location of the partitions is determined based upon a partition indicator included in the scalar instruction packet and a scalar instruction included in a partition is executed by a processing unit.
    Type: Application
    Filed: September 20, 2011
    Publication date: January 24, 2013
    Applicant: BROADCOM CORPORATION
    Inventors: Neil Bailey, Eben Upton
  • Publication number: 20110242113
    Abstract: In a graphics processing device, a plurality of processors write fragment shading results for order-dependent data to a buffer, according to the order in which the data is received. Fragment shading results for order-neutral data is written to the buffer one batch at a time. The order-dependent data comprises spatially overlapping data. Order-neutral data may not overlap. A scheduler controls the order of reception of one batch of data at a time by the processors. The order for receiving the order-dependent data may be determined. The plurality of processors may process the data in parallel. A writing order for writing results to a buffer from the processing in parallel, may be enforced. A portion of the processors may be instructed to wait before writing results to the buffer in a specified order. Processors signal when writing results to the buffer is complete.
    Type: Application
    Filed: November 24, 2010
    Publication date: October 6, 2011
    Inventors: Gary Keall, Giles Edkins, James Adams, Eben Upton
  • Publication number: 20110227920
    Abstract: A method and system are provided in which a first instruction associated with a graphics rendering operation may be executed in a shader processor, the shader processor may receive result information associated with an intermediate portion of the graphics rendering operation performed by a peripheral device operably coupled to a register file bus in the shader processor, and the shader processor may execute a second instruction associated with the graphics rendering operation based on the received result information. The register file bus may be utilized for handling execution of intermediate instructions associated with the intermediate portion of the graphics rendering operation. The peripheral device may be accessed via one or more register file addresses associated with the peripheral device. The peripheral device may be operably coupled to the shader processor via a FIFO.
    Type: Application
    Filed: August 27, 2010
    Publication date: September 22, 2011
    Inventors: James Adams, Gary Keall, Eben Upton, Giles Edkins
  • Publication number: 20110221743
    Abstract: A graphics processing device generates control lists for controlling processing of 3D graphics. Control lists comprise primitive data for the 3D graphics, pointers to primitive data and control data. Tags that correspond to records within the control lists may be utilized for the control of processing. The graphics processing device may comprise a 3D pipeline comprising parallel processors. Processing is performed on a tile by tile basis and comprises a tile binning phase and/or a tile rendering phase. The two phases of processing may be performed in parallel on different sets of data. Control lists comprise a main list and/or sub-lists, for example, tile lists. Control lists may comprise links to other lists. Processing control may advance through the control lists without interaction from a driver and/or from a processor that is external to the graphics processing device.
    Type: Application
    Filed: November 9, 2010
    Publication date: September 15, 2011
    Inventors: Gary Keall, Giles Edkins, Eben Upton, James Adams
  • Publication number: 20110216069
    Abstract: A graphics processing device may generate coordinates for vertices of graphics primitives in a view-space. Tiles are defined within the view-space and are associated with tile lists. Primitives and/or vertices which overlap a tile are determined. Tile lists comprise differentially encoded indices and/or spatial coordinates for overlapping primitives. The differential encoding may or may not be byte aligned. During tile mode graphics rendering, tile lists are utilized to reference vertex attributes and/or primitives. Graphics rendering comprises a tile binning phase and a tile rendering phase. The primitives may comprise a triangle and/or joined triangles that share one or more vertices. For multiple joined primitives, information about shared vertices may be encoded without repetition for each primitive. Coordinates and/or corresponding weights for new vertices are encoded in a tile list and utilized for interpolating properties of the new vertices based on attributes of the original vertices.
    Type: Application
    Filed: November 23, 2010
    Publication date: September 8, 2011
    Inventors: Gary Keall, Eben Upton, James Adams, Giles Edkins
  • Publication number: 20110148901
    Abstract: A method and system are provided in which one or more processors and/or circuits are operable to generate position information for a plurality of primitives utilizing a coordinate shader, one or more lists based on the generated position information, and rendering information for the plurality of primitives utilizing a vertex shader and the generated one or more lists. The generated one or more lists may comprise indices associated with one or more primitives from the plurality of primitives and with one or more tiles from a plurality of tiles in a screen plane. The position information and the one or more lists may be generated during a first rendering phase, and the rendering information may be generated during a second rendering phase different from the first rendering phase. The coordinate shader may perform a subset of the operations supported by the vertex shader.
    Type: Application
    Filed: August 25, 2010
    Publication date: June 23, 2011
    Inventors: James Adams, Gary Keall, Eben Upton, Giles Edkins
  • Publication number: 20110154377
    Abstract: Methods and systems for reducing communication during video processing utilizing merge buffering are disclosed and may include storing data in a merge buffer in the virtual machine layer in a wireless communication device comprising a virtual machine user layer, a native user layer, a kernel, and a video processor. The data may then be communicated to the kernel via the native user layer. The data may include function calls, and/or kernel remote procedure calls. The data may be communicated via an application programming interface. Video data may be processed in the video processor based on the communicated data. The virtual machine user layer may include a Java environment. The data may be communicated to the kernel via the native user layer when the merge buffer is full or filled to a predetermined level.
    Type: Application
    Filed: January 13, 2010
    Publication date: June 23, 2011
    Inventor: Eben Upton
  • Publication number: 20110154307
    Abstract: A method and system are provided in which one or more processors may be operable to generate an intermediate representation of a shader source code, wherein the intermediate representation comprises one or more whole-program data flow graph representations of the shader source code. The one or more processors may be operable to generate machine code based on the generated intermediate representation of the shader source code. The one or more whole-program data flow graph representations of the shader source code may be generated utilizing a compiler front end. The machine code may be generated utilizing a compiler back end. The generated machine code may be executable by a graphics processor. The generated machine code may be executable by a processor comprising a single-instruction multiple-data (SIMD) architecture. The generated machine code may be executable to perform coordinate and/or vertex shading of image primitives.
    Type: Application
    Filed: August 25, 2010
    Publication date: June 23, 2011
    Inventor: Eben Upton