Abstract: A computer-implemented method includes issuing an operation to a first core of a multicore processor. The operation includes transmitting a message from the first core to a second core of the multicore processor. Transmitting the message includes defining a payload including, providing the payload to a nest fabric of the first core and capturing the source address and the destination address, initiating a fetch to capture the message and store the message in a in a second cache of the second core, removing the message from the first core, and the second core fetching the message from the second cache, and returning a condition code to the first core without pulling the destination address back to the first core.

Abstract: Execution of an instruction includes obtaining software objects and loading instructions into a memory and storing the workload type attribute for each software object. The execution includes operations that during runtime, deploy a first hardware instruction to trigger a firmware process to sample, at each interval of timed pre-configured intervals, instructions from the sets of instructions of the one or more software objects being executed during the interval by one or more processors of the computing system. The operations include deploying a second hardware instruction to obtain and store samples from the firmware process in the memory. The operations include generating, based on analyzing the stored samples, execution parameters associated with each sample. The operations include determining accesses to the software libraries in the computing system, by workload type attribute. The operations automatically implement an action related to at least one software object in the computing system.

Abstract: Embodiments include in response to monitoring a processor during operation, detecting a first number of throttling amounts in the processor, determining that the first number of throttling amounts fulfills a first condition regarding a throttling amounts threshold, and modifying a voltage level of the processor by a first amount. Embodiments include in response to modifying the voltage level of the processor by the first amount, detecting a second number of throttling amounts in the processor, determining that the second number of throttling amounts fulfills a second condition regarding the throttling amounts threshold, and modifying the voltage level of the processor by a second amount.

Abstract: Embodiments include in response to monitoring a processor during operation, detecting a first number of core recovery events in the processor, determining that the first number of core recovery events fulfills a first condition for the first core recovery events threshold, and modifying a value of at least one droop sensor parameter of the processor by a first amount. The at least one droop sensor parameters affects a sensitivity to a voltage droop. In response to modifying the value of the droop sensor parameter by the first amount, a second number of core recovery events is detected in the processor. It is determined that the second number of core recovery events fulfills a second condition for a second core recovery events threshold, and the value of the at least one droop sensor parameter is modified by a second amount.

Abstract: A clock comparator sign control is used in a compare operation. A clock comparator sign control that determines whether unsigned arithmetic or signed arithmetic is to be used in a comparing operation is obtained. The clock comparator sign control is then used in a comparison of a value of a clock comparator and at least a portion of a value of a time-of-day clock to determine whether a selected action is to be recognized.

Abstract: Embodiments include in response to monitoring a processor during operation, detecting a first number of core recovery events in the processor, determining that the first number of core recovery events fulfills a first condition for the first core recovery events threshold, and modifying a value of at least one droop sensor parameter of the processor by a first amount. The at least one droop sensor parameters affects a sensitivity to a voltage droop. In response to modifying the value of the droop sensor parameter by the first amount, a second number of core recovery events is detected in the processor. It is determined that the second number of core recovery events fulfills a second condition for a second core recovery events threshold, and the value of the at least one droop sensor parameter is modified by a second amount.

Abstract: Embodiments include in response to monitoring a processor during operation, detecting a first number of throttling amounts in the processor, determining that the first number of throttling amounts fulfills a first condition regarding a throttling amounts threshold, and modifying a voltage level of the processor by a first amount. Embodiments include in response to modifying the voltage level of the processor by the first amount, detecting a second number of throttling amounts in the processor, determining that the second number of throttling amounts fulfills a second condition regarding the throttling amounts threshold, and modifying the voltage level of the processor by a second amount.

Abstract: A clock comparator sign control is used in a compare operation. A clock comparator sign control that determines whether unsigned arithmetic or signed arithmetic is to be used in a comparing operation is obtained. The clock comparator sign control is then used in a comparison of a value of a clock comparator and at least a portion of a value of a time-of-day clock to determine whether a selected action is to be recognized.

Abstract: A clock comparator sign control is used in a compare operation. A clock comparator sign control that determines whether unsigned arithmetic or signed arithmetic is to be used in a comparing operation is obtained. The clock comparator sign control is then used in a comparison of a value of a clock comparator and at least a portion of a value of a time-of-day clock to determine whether a selected action is to be recognized.

Abstract: Aspects of the present invention disclose a method for avoiding overvoltages of a processor chip. The method includes one or more processors identifying one or more processing units of a computing device. The method further includes determining respective activity levels of one or more processing elements of the one or more processing units of the computing device. The method further includes determining respective voltages of the one or more processing units of the computing device. The method further includes regulating the respective voltages of the one or more processing units of the computing device based at least in part on the respective activity levels of the one or more processing elements.

Abstract: Aspects of the present invention disclose a method for avoiding overvoltages of a processor chip. The method includes one or more processors identifying one or more processing units of a computing device. The method further includes determining respective activity levels of one or more processing elements of the one or more processing units of the computing device. The method further includes determining respective voltages of the one or more processing units of the computing device. The method further includes regulating the respective voltages of the one or more processing units of the computing device based at least in part on the respective activity levels of the one or more processing elements.

Abstract: According to one or more embodiments of the present invention, a computer-implemented method includes detecting an abnormal event in operation of a first partition from a plurality of partitions of a computer server, the first partition being associated with a set of processors of the computer server and with a set of computing resources of the computer server. The method further includes in response, determining the set of processors associated with the first partition. The method further includes adjusting one or more settings of the set of processors to increase the set of computing resources associated with the first partition to complete the abnormal event.

Abstract: According to one or more embodiments of the present invention, a computer-implemented method includes detecting an abnormal event in operation of a first partition from a plurality of partitions of a computer server, the first partition being associated with a set of processors of the computer server and with a set of computing resources of the computer server. The method further includes in response, determining the set of processors associated with the first partition. The method further includes adjusting one or more settings of the set of processors to increase the set of computing resources associated with the first partition to complete the abnormal event.

Abstract: An aspect includes performing, for each of a plurality of hardware threads executing on a plurality of cores in a (SMP) computer system, receiving a value of a timer corresponding to the hardware thread, the timer counting a number of clock cycles since a last reset of the timer. The value of the timer is compared to a threshold value for the hardware thread, where the threshold value specifies a number of clock cycles. Based on the value of the timer meeting the threshold value, a control signal is sent to cause all hardware threads currently executing on the core to halt execution and data describing a state of the core is logged. Each of the timers corresponding to each of the plurality of hardware threads are configured to be reset, paused, and restarted independently of each of the other timers.

Abstract: A clock comparator sign control is used in a compare operation. A clock comparator sign control that determines whether unsigned arithmetic or signed arithmetic is to be used in a comparing operation is obtained. The clock comparator sign control is then used in a comparison of a value of a clock comparator and at least a portion of a value of a time-of-day clock to determine whether a selected action is to be recognized.

Abstract: A clock comparator sign control is used in a compare operation. A clock comparator sign control that determines whether unsigned arithmetic or signed arithmetic is to be used in a comparing operation is obtained. The clock comparator sign control is then used in a comparison of a value of a clock comparator and at least a portion of a value of a time-of-day clock to determine whether a selected action is to be recognized.

Abstract: An aspect includes performing, for each of a plurality of hardware threads executing on a plurality of cores in a (SMP) computer system, receiving a value of a timer corresponding to the hardware thread, the timer counting a number of clock cycles since a last reset of the timer. The value of the timer is compared to a threshold value for the hardware thread, where the threshold value specifies a number of clock cycles. Based on the value of the timer meeting the threshold value, a control signal is sent to cause all hardware threads currently executing on the core to halt execution and data describing a state of the core is logged. Each of the timers corresponding to each of the plurality of hardware threads are configured to be reset, paused, and restarted independently of each of the other timers.

Abstract: A clock comparator sign control is used in a compare operation. A clock comparator sign control that determines whether unsigned arithmetic or signed arithmetic is to be used in a comparing operation is obtained. The clock comparator sign control is then used in a comparison of a value of a clock comparator and at least a portion of a value of a time-of-day clock to determine whether a selected action is to be recognized.

Abstract: A system and method for generating a timestamp without processor core execution stall are provided. For example, the method includes generating, using a first processor core, a timestamp. The method also includes preventing, using the first processor core, a second processor core from accessing the timestamp for a minimum time granularity interval. The time granularity interval provides a delay such that the timestamp generated by the first processor core is earlier in time than a second processor core timestamp.

Abstract: An indication of time that indicates at least one of the current day and the current time is received. It is determined that a raw interval pulse transmitted by a first oscillator should be adjusted based, at least partly, on the indication of time. In response to determining that the raw interval pulse should be adjusted, a steered time interval pulse is generated based, at least partly, on the raw time interval pulse and the indication of time. The steered time interval pulse is distributed to a plurality of hardware components.