Patents by Inventor Eberhard Engler
Eberhard Engler has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11953982Abstract: Embodiments include in response to monitoring a processor during operation, detecting a first number of core recovery events in the processor, determining that the first number of core recovery events fulfills a first condition for the first core recovery events threshold, and modifying a value of at least one droop sensor parameter of the processor by a first amount. The at least one droop sensor parameters affects a sensitivity to a voltage droop. In response to modifying the value of the droop sensor parameter by the first amount, a second number of core recovery events is detected in the processor. It is determined that the second number of core recovery events fulfills a second condition for a second core recovery events threshold, and the value of the at least one droop sensor parameter is modified by a second amount.Type: GrantFiled: July 19, 2022Date of Patent: April 9, 2024Assignee: International Business Machines CorporationInventors: Alejandro Alberto Cook Lobo, Andrew A. Turner, Christian Jacobi, Eberhard Engler, Edward C. McCain, Kevin P. Low, Phillip John Restle, Pradeep Bhadravati Parashurama, Tobias Webel, Alper Buyuktosunoglu, Karl Evan Smock Anderson, Sean Michael Carey, Kennedy Cheruiyot, Daniel Kiss, Isidore G. Bendrihem, Ian Krispin Carmichael
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Patent number: 11934220Abstract: A clock comparator sign control is used in a compare operation. A clock comparator sign control that determines whether unsigned arithmetic or signed arithmetic is to be used in a comparing operation is obtained. The clock comparator sign control is then used in a comparison of a value of a clock comparator and at least a portion of a value of a time-of-day clock to determine whether a selected action is to be recognized.Type: GrantFiled: October 20, 2021Date of Patent: March 19, 2024Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Eberhard Engler, Dan F. Greiner, Michel H. T. Hack, Timothy J. Slegel, Joachim von Buttlar
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Publication number: 20240028095Abstract: Embodiments include in response to monitoring a processor during operation, detecting a first number of throttling amounts in the processor, determining that the first number of throttling amounts fulfills a first condition regarding a throttling amounts threshold, and modifying a voltage level of the processor by a first amount. Embodiments include in response to modifying the voltage level of the processor by the first amount, detecting a second number of throttling amounts in the processor, determining that the second number of throttling amounts fulfills a second condition regarding the throttling amounts threshold, and modifying the voltage level of the processor by a second amount.Type: ApplicationFiled: July 19, 2022Publication date: January 25, 2024Inventors: Tobias Webel, Alejandro Alberto Cook Lobo, Andrew A. Turner, CHRISTIAN JACOBI, Eberhard Engler, Edward C. McCain, Kevin P. Low, Phillip John Restle, Pradeep Bhadravati Parashurama, Alper Buyuktosunoglu, KARL EVAN SMOCK ANDERSON, Sean Michael Carey, KENNEDY CHERUIYOT, Daniel Kiss, Isidore G. Bendrihem, Eric Jason Fluhr, IAN KRISPIN CARMICHAEL, Gregory Scott Still
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Publication number: 20240028447Abstract: Embodiments include in response to monitoring a processor during operation, detecting a first number of core recovery events in the processor, determining that the first number of core recovery events fulfills a first condition for the first core recovery events threshold, and modifying a value of at least one droop sensor parameter of the processor by a first amount. The at least one droop sensor parameters affects a sensitivity to a voltage droop. In response to modifying the value of the droop sensor parameter by the first amount, a second number of core recovery events is detected in the processor. It is determined that the second number of core recovery events fulfills a second condition for a second core recovery events threshold, and the value of the at least one droop sensor parameter is modified by a second amount.Type: ApplicationFiled: July 19, 2022Publication date: January 25, 2024Inventors: Alejandro Alberto Cook Lobo, Andrew A. Turner, CHRISTIAN JACOBI, Eberhard Engler, Edward C. McCain, Kevin P. Low, Phillip John Restle, Pradeep Bhadravati Parashurama, Tobias Webel, Alper Buyuktosunoglu, KARL EVAN SMOCK ANDERSON, Sean Michael Carey, KENNEDY CHERUIYOT, Daniel Kiss, Isidore G. Bendrihem, IAN KRISPIN CARMICHAEL
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Publication number: 20220035399Abstract: A clock comparator sign control is used in a compare operation. A clock comparator sign control that determines whether unsigned arithmetic or signed arithmetic is to be used in a comparing operation is obtained. The clock comparator sign control is then used in a comparison of a value of a clock comparator and at least a portion of a value of a time-of-day clock to determine whether a selected action is to be recognized.Type: ApplicationFiled: October 20, 2021Publication date: February 3, 2022Inventors: Eberhard Engler, Dan F. Greiner, Michel H. T. Hack, Timothy J. Slegel, Joachim von Buttlar
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Patent number: 11199870Abstract: A clock comparator sign control is used in a compare operation. A clock comparator sign control that determines whether unsigned arithmetic or signed arithmetic is to be used in a comparing operation is obtained. The clock comparator sign control is then used in a comparison of a value of a clock comparator and at least a portion of a value of a time-of-day clock to determine whether a selected action is to be recognized.Type: GrantFiled: August 19, 2019Date of Patent: December 14, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Eberhard Engler, Dan F. Greiner, Michel H. T. Hack, Timothy J. Slegel, Joachim von Buttlar
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Patent number: 11169841Abstract: Aspects of the present invention disclose a method for avoiding overvoltages of a processor chip. The method includes one or more processors identifying one or more processing units of a computing device. The method further includes determining respective activity levels of one or more processing elements of the one or more processing units of the computing device. The method further includes determining respective voltages of the one or more processing units of the computing device. The method further includes regulating the respective voltages of the one or more processing units of the computing device based at least in part on the respective activity levels of the one or more processing elements.Type: GrantFiled: March 17, 2020Date of Patent: November 9, 2021Assignee: Internationl Business Machines CorporationInventors: K Paul Muller, William V. Huott, Eberhard Engler, Christopher Raymond Conklin, Stephanie Lehrer, Andrew A. Turner
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Publication number: 20210294640Abstract: Aspects of the present invention disclose a method for avoiding overvoltages of a processor chip. The method includes one or more processors identifying one or more processing units of a computing device. The method further includes determining respective activity levels of one or more processing elements of the one or more processing units of the computing device. The method further includes determining respective voltages of the one or more processing units of the computing device. The method further includes regulating the respective voltages of the one or more processing units of the computing device based at least in part on the respective activity levels of the one or more processing elements.Type: ApplicationFiled: March 17, 2020Publication date: September 23, 2021Inventors: K Paul Muller, William V. Huott, Eberhard Engler, Christopher Raymond Conklin, Stephanie Lehrer, Andrew A. Turner
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Patent number: 10884845Abstract: According to one or more embodiments of the present invention, a computer-implemented method includes detecting an abnormal event in operation of a first partition from a plurality of partitions of a computer server, the first partition being associated with a set of processors of the computer server and with a set of computing resources of the computer server. The method further includes in response, determining the set of processors associated with the first partition. The method further includes adjusting one or more settings of the set of processors to increase the set of computing resources associated with the first partition to complete the abnormal event.Type: GrantFiled: November 8, 2018Date of Patent: January 5, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Peter Sutton, David Lee, Eberhard Engler, Thomas Rozmus
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Publication number: 20200151049Abstract: According to one or more embodiments of the present invention, a computer-implemented method includes detecting an abnormal event in operation of a first partition from a plurality of partitions of a computer server, the first partition being associated with a set of processors of the computer server and with a set of computing resources of the computer server. The method further includes in response, determining the set of processors associated with the first partition. The method further includes adjusting one or more settings of the set of processors to increase the set of computing resources associated with the first partition to complete the abnormal event.Type: ApplicationFiled: November 8, 2018Publication date: May 14, 2020Inventors: Peter Sutton, David Lee, Eberhard Engler, Thomas Rozmus
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Patent number: 10579499Abstract: An aspect includes performing, for each of a plurality of hardware threads executing on a plurality of cores in a (SMP) computer system, receiving a value of a timer corresponding to the hardware thread, the timer counting a number of clock cycles since a last reset of the timer. The value of the timer is compared to a threshold value for the hardware thread, where the threshold value specifies a number of clock cycles. Based on the value of the timer meeting the threshold value, a control signal is sent to cause all hardware threads currently executing on the core to halt execution and data describing a state of the core is logged. Each of the timers corresponding to each of the plurality of hardware threads are configured to be reset, paused, and restarted independently of each of the other timers.Type: GrantFiled: April 4, 2017Date of Patent: March 3, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Eberhard Engler, Christian Jacobi, Timothy J. Slegel, Scott B. Swaney
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Publication number: 20190377379Abstract: A clock comparator sign control is used in a compare operation. A clock comparator sign control that determines whether unsigned arithmetic or signed arithmetic is to be used in a comparing operation is obtained. The clock comparator sign control is then used in a comparison of a value of a clock comparator and at least a portion of a value of a time-of-day clock to determine whether a selected action is to be recognized.Type: ApplicationFiled: August 19, 2019Publication date: December 12, 2019Inventors: Eberhard Engler, Dan F. Greiner, Michel H. T. Hack, Timothy J. Slegel, Joachim von Buttlar
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Patent number: 10423191Abstract: A clock comparator sign control is used in a compare operation. A clock comparator sign control that determines whether unsigned arithmetic or signed arithmetic is to be used in a comparing operation is obtained. The clock comparator sign control is then used in a comparison of a value of a clock comparator and at least a portion of a value of a time-of-day clock to determine whether a selected action is to be recognized.Type: GrantFiled: January 19, 2017Date of Patent: September 24, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Eberhard Engler, Dan F. Greiner, Michel H. T. Hack, Timothy J. Slegel, Joachim von Buttlar
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Publication number: 20180285147Abstract: An aspect includes performing, for each of a plurality of hardware threads executing on a plurality of cores in a (SMP) computer system, receiving a value of a timer corresponding to the hardware thread, the timer counting a number of clock cycles since a last reset of the timer. The value of the timer is compared to a threshold value for the hardware thread, where the threshold value specifies a number of clock cycles. Based on the value of the timer meeting the threshold value, a control signal is sent to cause all hardware threads currently executing on the core to halt execution and data describing a state of the core is logged. Each of the timers corresponding to each of the plurality of hardware threads are configured to be reset, paused, and restarted independently of each of the other timers.Type: ApplicationFiled: April 4, 2017Publication date: October 4, 2018Inventors: Eberhard Engler, Christian Jacobi, Timothy J. Slegel, Scott B. Swaney
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Publication number: 20180203480Abstract: A clock comparator sign control is used in a compare operation. A clock comparator sign control that determines whether unsigned arithmetic or signed arithmetic is to be used in a comparing operation is obtained. The clock comparator sign control is then used in a comparison of a value of a clock comparator and at least a portion of a value of a time-of-day clock to determine whether a selected action is to be recognized.Type: ApplicationFiled: January 19, 2017Publication date: July 19, 2018Inventors: Eberhard Engler, Dan F. Greiner, Michel H. T. Hack, Timothy J. Slegel, Joachim von Buttlar
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Patent number: 9720441Abstract: A system and method for generating a timestamp without processor core execution stall are provided. For example, the method includes generating, using a first processor core, a timestamp. The method also includes preventing, using the first processor core, a second processor core from accessing the timestamp for a minimum time granularity interval. The time granularity interval provides a delay such that the timestamp generated by the first processor core is earlier in time than a second processor core timestamp.Type: GrantFiled: September 30, 2016Date of Patent: August 1, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Eberhard Engler, Christian Jacobi, Martin Recktenwald, Timothy J. Slegel
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Patent number: 9104364Abstract: An indication of time that indicates at least one of the current day and the current time is received. It is determined that a raw interval pulse transmitted by a first oscillator should be adjusted based, at least partly, on the indication of time. In response to determining that the raw interval pulse should be adjusted, a steered time interval pulse is generated based, at least partly, on the raw time interval pulse and the indication of time. The steered time interval pulse is distributed to a plurality of hardware components.Type: GrantFiled: November 15, 2012Date of Patent: August 11, 2015Assignee: International Business Machines CorporationInventors: Eberhard Engler, Guenter Gerwig, Willm Hinrichs, Barinjato Ramanandray
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Publication number: 20140136877Abstract: An apparatus comprising a first oscillator, a time source controller coupled with the first oscillator and corrected time interval counters coupled with the time source controller. The first oscillator is configured to transmit a raw time interval pulse at regular or near regular intervals. The time source controller is configured to receive an indication of time that indicates at least one of the current day and the current time and to determine that the raw interval pulse should be adjusted based on the indication of time. The time source controller is also configured to generate a steered time interval pulse based, at least partly, on the raw time interval pulse and the indication of time, and distribute the steered time interval pulse to a plurality of hardware components. The time interval counters are configured to host a time value based on the output from the time source controller.Type: ApplicationFiled: November 15, 2012Publication date: May 15, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Eberhard Engler, Guenter Gerwig, Willm Hinrichs, Barinjato Ramanandray
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Patent number: 8438415Abstract: A system, method and computer program product for steering a time-of-day (TOD) clock for a computer system having a physical clock providing a time base for executing operations that is stepped to a common oscillator. The method includes receiving, at a processing unit, a request to change a clock steering rate used to control a TOD-clock offset value for the processing unit, the TOD-clock offset defined as a function of a start time (s), a base offset (b), and a steering rate (r). The unit schedules a next episode start time with which to update the TOD-clock offset value. After updating TOD-clock offset value (d) at the scheduled time, TOD-clock offset value is added to a physical-clock value (Tr) value to obtain a logical TOD-clock value (Tb), where the logical TOD-clock value is adjustable without adjusting a stepping rate of the oscillator.Type: GrantFiled: February 22, 2012Date of Patent: May 7, 2013Assignee: International Business Machines CorporationInventors: Eberhard Engler, Mark S. Farrell, Klaus Meissner, Mark A. Check, Evangelyn K. Smith
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Publication number: 20120246508Abstract: A method is presented for continuously providing a high precision system clock associated with a processing core, wherein the system clock includes a host clock register that is incremented via a high precision oscillator, the method includes: providing a firmware clock register, incrementing the firmware clock register based on the host clock register being incremented, monitoring for failures of the host clock register, and during a failure of the host clock register continuously incrementing the firmware clock register by means of timing signals of the processing core, and upon receipt of a request to provide a clock value, providing the content of the host clock register if no failure was detected, or if failure was detected, providing the content of the firmware clock register.Type: ApplicationFiled: February 15, 2012Publication date: September 27, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Eberhard ENGLER, Guenter GERWIG, Frank LEHNERT, Klaus MEISSNER, Joachim von BUTTLAR