Abstract: An address converter for converting first addresses into second addresses which are fed to a memory of the data processing device, where the first addresses contain first and second address words and the second addresses contain third and fourth address words, the address words representing binary numbers, employs a comparator which is supplied with the first address word and a predetermined binary number and which is responsive thereto to emit a binary signal which assumes a first or a second binary value when the first address word is smaller than, or is not smaller than, respectively, the binary number, a transfer switch which assumes a first condition and a second condition when the binary signal assumes the first and second binary values, respectively, and which in the first and second positions, respectively, switches through the first address word or the binary number as a third address word, respectively, and an allocator which is supplied with the first and the second address words and which emits th