Patents by Inventor Ebo H. Croffie

Ebo H. Croffie has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9188848
    Abstract: The present invention provides methods and apparatus for accomplishing optical direct write phase shift lithography. A lithography system and method are provided wherein a mirror array is configured to generate vortex phase shift optical patterns that are directed onto a photosensitive layer of a substrate. The lithography methods and systems facilitate pattern transfer using such vortex phase shift exposure patterns.
    Type: Grant
    Filed: December 20, 2012
    Date of Patent: November 17, 2015
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Nicholas K. Eib, Ebo H. Croffie, Neal P. Callan
  • Publication number: 20130107240
    Abstract: The present invention provides methods and apparatus for accomplishing optical direct write phase shift lithography. A lithography system and method are provided wherein a mirror array is configured to generate vortex phase shift optical patterns that are directed onto a photosensitive layer of a substrate. The lithography methods and systems facilitate pattern transfer using such vortex phase shift exposure patterns.
    Type: Application
    Filed: December 20, 2012
    Publication date: May 2, 2013
    Applicant: LSI CORPORATION
    Inventors: Nicholas K. Eib, Ebo H. Croffie, Neal P. Callan
  • Patent number: 8377633
    Abstract: The present invention provides methods and apparatus for accomplishing optical direct write phase shift lithography. A lithography system and method are provided wherein a mirror array is configured to generate vortex phase shift optical patterns that are directed onto a photosensitive layer of a substrate. The lithography methods and systems facilitate pattern transfer using such vortex phase shift exposure patterns.
    Type: Grant
    Filed: October 5, 2011
    Date of Patent: February 19, 2013
    Assignee: LSI Corporation
    Inventors: Nicholas K. Eib, Ebo H. Croffie, Neal P. Callan
  • Publication number: 20120038896
    Abstract: The present invention provides methods and apparatus for accomplishing optical direct write phase shift lithography. A lithography system and method are provided wherein a mirror array is configured to generate vortex phase shift optical patterns that are directed onto a photosensitive layer of a substrate. The lithography methods and systems facilitate pattern transfer using such vortex phase shift exposure patterns.
    Type: Application
    Filed: October 5, 2011
    Publication date: February 16, 2012
    Applicant: LSI CORPORATION
    Inventors: Nicholas K. Eib, Ebo H. Croffie, Neal P. Callan
  • Patent number: 8057963
    Abstract: The present invention provides methods and apparatus for accomplishing a optical direct write phase shift lithography. A lithography system and method are provided wherein a mirror array is configured to generate vortex phase shift optical patterns that are directed onto a photosensitive layer of a substrate. The lithography methods and systems facilitate pattern transfer using such vortex phase shift exposure patterns.
    Type: Grant
    Filed: December 14, 2004
    Date of Patent: November 15, 2011
    Assignee: LSI Corporation
    Inventors: Nicholas K. Eib, Ebo H. Croffie, Neal P. Callan
  • Patent number: 7494752
    Abstract: A method and system for utilizing a simplified resist process model to perform optical and process corrections. More specifically, the present invention provides a fast and easy post exposure bake (PEB) effects calculation which can be used in connection with OPC. The model can be used to increase OPC modeling accuracy, by taking PEB effects into consideration, without incurring a large overhead increase due to PEB calculation cost. The method includes providing an image, calculating initial acid concentration and adding acid concentration contours to the image, calculating deprotection concentration and adding deprotection concentration contours to the image, determining latent image contour without diffusion, moving the latent image contour in a direction of lower deprotection concentration to provide the final latent image, performing OPC on the chemically amplified resist using edge movement based on the final latent image, and repeating the process to obtain convergence.
    Type: Grant
    Filed: February 11, 2005
    Date of Patent: February 24, 2009
    Assignee: LSI Corporation
    Inventor: Ebo H. Croffie
  • Patent number: 7458060
    Abstract: A method and system are provided for analyzing process window compliance of an integrated circuit design. Aspects of the present invention include identifying layout pattern configurations that have process windows that fail to meet respective local performance specifications; searching for any layout pattern configurations in a design that substantially match any of the identified layout pattern configurations; and modifying any matching layout pattern configurations found in the design to make the layout pattern configurations compliant with their respective process windows.
    Type: Grant
    Filed: December 30, 2005
    Date of Patent: November 25, 2008
    Assignee: LSI Logic Corporation
    Inventors: Ebo H. Croffie, Nicolas K. Eib
  • Patent number: 7372547
    Abstract: The present invention provides methods and apparatus for accomplishing a phase shift lithography process using a off axis light to reduce the effect of zero order light to improve the process window for maskless phase shift lithography systems and methodologies. A lithography system is provided. The lithography system provided uses off axis light beams projected onto a mirror array configured to generate a phase shift optical image pattern. This pattern is projected onto a photoimageable layer formed on the target substrate to facilitate pattern transfer.
    Type: Grant
    Filed: December 14, 2004
    Date of Patent: May 13, 2008
    Assignee: LSI Corporation
    Inventors: Nicholas K. Eib, Ebo H. Croffie, Neal P. Callan
  • Patent number: 7325222
    Abstract: A method for verifying reticle enhancement technique latent image sensitivity to mask manufacturing errors. The method includes the steps of revising a polygon based on mask CD distributions to provide a virtual mask, imaging the virtual mask to obtain response function statistical parameters, and comparing the statistical parameters to process tolerance requirements. Preferably, the method includes the steps of simulating an aerial and/or latent image of the virtual mask, calculating response functions based on the mask image simulation, collecting measurements and calculating statistical parameters based on the response functions, and comparing the statistical parameters with design rule requirements (i.e., for DI yield percentage for required mask manufacturing specification). The virtual mask is obtained by using mask CD distribution to induce statistical variations to layouts which have passed through the conventional OPC procedure.
    Type: Grant
    Filed: March 12, 2004
    Date of Patent: January 29, 2008
    Assignee: LSI Logic Corporation
    Inventors: Nadya G. Strelkova, Ebo H. Croffie, John V. Jensen
  • Patent number: 7264906
    Abstract: A method and system of optimizing the illumination of a mask in a photolithography process. A specific, preferred method includes the steps of: loading minimum design rules of a layout, loading exposure latitude constraints, loading mask error constraints, loading initial illumination conditions, simulating current illumination conditions, obtaining dose-to-print threshold from the minimum design rules (i.e., lines-and-space feature), applying OPC on the layout using the dose-to-print threshold, calculating DOF using the exposure latitude and mask error constraints, changing the illumination conditions in order to attempt to maximize common DOF with the exposure latitude and mask error constraints, and continuing the process until maximum common DOF is obtained.
    Type: Grant
    Filed: March 5, 2004
    Date of Patent: September 4, 2007
    Assignee: LSI Corporation
    Inventors: Ebo H. Croffie, Nicholas K. Eib, Mario Garza, Paul Filseth, Lav D. Ivanovic
  • Patent number: 7189498
    Abstract: The present invention provides methods and apparatus for accomplishing a strong phase shift direct write lithography process using reconfigurable optical mirrors. A maskless lithography system is provided. The maskless direct-write lithography system provided uses an array of mirrors configured to operate in a tilting mode, a piston-displacement mode, or both in combination. The controlled mirror array is used to generate strong phase shift optical patterns which are directed onto a photoimageable layer of a substrate in order to facilitate pattern transfer. In order to avoid constraining the system to forming edges of patterns aligned with the array of mirrors, gray-scale techniques are used for subpixel feature placement.
    Type: Grant
    Filed: November 19, 2004
    Date of Patent: March 13, 2007
    Assignee: LSI Logic Corporation
    Inventors: Nicholas K. Eib, Ebo H. Croffie, Neal P. Callan
  • Patent number: 7001695
    Abstract: A method and apparatus for improving resolution in photolithography. The method includes steps of mapping a first phase onto a first mask, mapping a second phase onto a second mask, and mapping a trim onto the first mask or second mask (or both). Specifically, the first mask may include Phase1 mapped to 0/180 phase, and the second mask may include Phase2 and trim mapped to 0/180 phase. A set of masks consistent with the foregoing is provided.
    Type: Grant
    Filed: May 9, 2003
    Date of Patent: February 21, 2006
    Assignee: LSI Logic Corporation
    Inventors: Ebo H. Croffie, Christopher Neville
  • Publication number: 20040224239
    Abstract: A method and apparatus for improving resolution in photolithography. The method includes steps of mapping a first phase onto a first mask, mapping a second phase onto a second mask, and mapping a trim onto the first mask or second mask (or both). Specifically, the first mask may include Phase1 mapped to 0/180 phase, and the second mask may include Phase2 and trim mapped to 0/180 phase. A set of masks consistent with the foregoing is provided.
    Type: Application
    Filed: May 9, 2003
    Publication date: November 11, 2004
    Inventors: Ebo H. Croffie, Christopher Neville