Patents by Inventor Ebony Lynn Mays

Ebony Lynn Mays has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230402389
    Abstract: A memory array including integrated word line (WL) contact structures are disclosed. The memory array comprises a plurality of WLs that includes at least a first WL and a second WL. An integrated WL contact structure includes a first WL contact and a second WL contact for the first WL and the second WL, respectively. The second WL contact extends through the first WL contact. For example, the second WL contact is nested within the first WL contact. An intervening isolation material isolates the second WL contact from the first WL contact. In an example, the second WL contact extends through a hole in the first WL to reach the second WL. The isolation material isolates the second WL contact from sidewalls of the hole in the first WL.
    Type: Application
    Filed: August 18, 2023
    Publication date: December 14, 2023
    Inventors: Nanda Kumar Chakravarthi, Kwame Nkrumah Eason, Abhinav Tripathi, Ebony Lynn MAYS, Jessica Sevanne Kachian, Ralf Buengener
  • Publication number: 20230033086
    Abstract: A memory array including a varying width channel is disclosed. The array includes a plurality of WLs, which are above a layer, where the layer can be, for example, a Select Gate Source (SGS) of the memory array, or an isolation layer to isolate a first deck of the array from a second deck of the array. The channel extends through the plurality of word lines and at least partially through the layer. In an example, the channel comprises a first region and a second region. The first region of the channel has a first width that is at least 1 nm different from a second width of the second region of the channel. In an example, the first region extends through the plurality of word lines, and the second region extends through at least a part of the layer underneath the plurality of word lines. In one case, the first width is at least 1 nm less than a second width of the second region of the channel.
    Type: Application
    Filed: February 7, 2020
    Publication date: February 2, 2023
    Inventors: Chen WANG, Dipanjan BASU, Richard FASTOW, Dimitri KIOUSSIS, Yi LI, Ebony Lynn MAYS, Dimitrios PAVLOPOULOS, Junyen TEWG
  • Publication number: 20210143100
    Abstract: A memory array including integrated word line (WL) contact structures are disclosed. The memory array comprises a plurality of WLs that includes at least a first WL and a second WL. An integrated WL contact structure includes a first WL contact and a second WL contact for the first WL and the second WL, respectively. The second WL contact extends through the first WL contact. For example, the second WL contact is nested within the first WL contact. An intervening isolation material isolates the second WL contact from the first WL contact. In an example, the second WL contact extends through a hole in the first WL to reach the second WL. The isolation material isolates the second WL contact from sidewalls of the hole in the first WL.
    Type: Application
    Filed: November 12, 2019
    Publication date: May 13, 2021
    Applicant: Intel Corporation
    Inventors: Nanda Kumar Chakravarthi, Kwame Nkrumah Eason, Abhinav Tripathi, Ebony Lynn Mays, Jessica Sevanne Kachian, Ralf Buengener
  • Patent number: 7098476
    Abstract: A novel air-gap-containing interconnect wiring structure is described incorporating a solid low-k dielectric in the via levels, and a composite solid plus air-gap dielectric in the wiring levels. Also provided is a method for forming such an interconnect structure. The method is readily scalable to interconnect structures containing multiple wiring levels, and is compatible with Dual Damascene Back End of the Line (BEOL) processing.
    Type: Grant
    Filed: September 24, 2004
    Date of Patent: August 29, 2006
    Assignee: International Business Machines Corporation
    Inventors: Katherina E. Babich, Roy Arthur Carruthers, Timothy Joseph Dalton, Alfred Grill, Jeffrey Curtis Hedrick, Christopher Vincent Jahnes, Ebony Lynn Mays, Laurent Perraud, Sampath Purushothaman, Katherine Lynn Saenger
  • Patent number: 6815329
    Abstract: A novel air-gap-containing interconnect wiring structure is described incorporating a solid low-k dielectric in the via levels, and a composite solid plus air-gap dielectric in the wiring levels. Also provided is a method for forming such an interconnect structure. The method is readily scalable to interconnect structures containing multiple wiring levels, and is compatible with Dual Damascene Back End of the Line (BEOL) processing.
    Type: Grant
    Filed: April 2, 2002
    Date of Patent: November 9, 2004
    Assignee: International Business Machines Corporation
    Inventors: Katherina E. Babich, Roy Arthur Carruthers, Timothy Joseph Dalton, Alfred Grill, Jeffrey Curtis Hedrick, Christopher Vincent Jahnes, Ebony Lynn Mays, Laurent Perraud, Sampath Purushothaman, Katherine Lynn Saenger
  • Publication number: 20020158337
    Abstract: A novel air-gap-containing interconnect wiring structure is described incorporating a solid low-k dielectric in the via levels, and a composite solid plus air-gap dielectric in the wiring levels. Also provided is a method for forming such an interconnect structure. The method is readily scalable to interconnect structures containing multiple wiring levels, and is compatible with Dual Damascene Back End of the Line (BEOL) processing.
    Type: Application
    Filed: April 2, 2002
    Publication date: October 31, 2002
    Inventors: Katherina E. Babich, Roy Arthur Carruthers, Timothy Joseph Dalton, Alfred Grill, Jeffrey Curtis Hedrick, Christopher Vincent Jahnes, Ebony Lynn Mays, Laurent Perraud, Sampath Purushothaman, Katherine Lynn Saenger