Abstract: A method to adaptively and dynamically set a bias scheme of a crossbar array for a write operation includes: performing a read-before-write operation to determine a number of cells n to be written during a write operation; comparing n to a predetermined threshold value to determine an efficient bias scheme; setting at least one voltage regulator to provide a bias voltage according to the efficient bias scheme; and performing the write operation. A method to determine threshold value to determine an efficient bias scheme of a crossbar array and an energy efficient crossbar array device are also described.

Abstract: A base element for switching a magnetization state of a nanomagnet includes a heavy-metal nanostrip having a surface. The heavy-metal nanostrip includes at least a first layer including a heavy metal and a second layer which includes a different heavy-metal. A ferromagnetic nanomagnet is disposed adjacent to the surface. The ferromagnetic nanomagnet includes a shape having a long axis and a short axis, the ferromagnetic nanomagnet having both a perpendicular-to-the-plane anisotropy Hkz and an in-plane anisotropy Hkx and the ferromagnetic nanomagnet having a first magnetization equilibrium state and a second magnetization equilibrium state. The first magnetization equilibrium state or the second magnetization equilibrium state is settable by a flow of electrical charge through the heavy-metal nanostrip. A direction of the flow of electrical charge through the heavy-metal nanostrip includes an angle ? with respect to the short axis of the nanomagnet.

Abstract: A base element for switching a magnetization state of a nanomagnet includes a heavy-metal nanostrip having a surface. A ferromagnetic nanomagnet is disposed adjacent to the surface. The ferromagnetic nanomagnet includes a shape having a long axis and a short axis. The ferromagnetic nanomagnet has both a perpendicular-to-the-plane anisotropy Hkz and an in-plane anisotropy Hkx and the ferromagnetic nanomagnet has a first magnetization equilibrium state and a second magnetization equilibrium state. The first magnetization equilibrium state or the second magnetization equilibrium state is settable by a flow of electrical charge through the heavy-metal nanostrip. A direction of flow of the electrical charge through the heavy-metal nanostrip includes an angle ? with respect to the short axis of the nanomagnet.

Abstract: An energy efficient rapid single flux quantum (ERSFQ) logic register wheel includes a circular shift register having a plurality of destructive read out (DRO) cells. Each entry of the circular shift register includes a data block, a tag, and a valid bit. A compare and control logic is coupled to the circular shift register to compare a source specifier or a destination register specifier against a register tag stored in the wheel following each cycle of the register wheel. At least one or more read ports and at least one or more write ports are coupled to the circular shift register to write to or to read from a different entry each in the register wheel following each cycle of the register wheel. A RSFQ clearable FIFO with flushing and a crosspoint memory topology for integrating MRAM devices with ERSFQ circuits are also described.

Abstract: A base element for switching a magnetization state of a nanomagnet includes a heavy-metal strip having a surface. A ferromagnetic nanomagnet is disposed adjacent to the surface. The ferromagnetic nanomagnet has a first magnetization equilibrium state and a second magnetization equilibrium state. The first magnetization equilibrium state or the second magnetization equilibrium state is settable in an absence of an external magnetic field by a flow of electrical charge through the heavy-metal strip. A method for switching a magnetization state of a nanomagnet is also described.

Abstract: An energy efficient rapid single flux quantum (ERSFQ) logic register wheel includes a circular shift register having a plurality of destructive read out (DRO) cells. Each entry of the circular shift register includes a data block, a tag, and a valid bit. A compare and control logic is coupled to the circular shift register to compare a source specifier or a destination register specifier against a register tag stored in the wheel following each cycle of the register wheel. At least one or more read ports and at least one or more write ports are coupled to the circular shift register to write to or to read from a different entry each in the register wheel following each cycle of the register wheel. A RSFQ clearable FIFO with flushing and a crosspoint memory topology for integrating MRAM devices with ERSFQ circuits are also described.

Abstract: A base element for switching a magnetization state of a nanomagnet includes a heavy-metal strip having a surface. A ferromagnetic nanomagnet is disposed adjacent to the surface. The ferromagnetic nanomagnet has a first magnetization equilibrium state and a second magnetization equilibrium state. The first magnetization equilibrium state or the second magnetization equilibrium state is settable in an absence of an external magnetic field by a flow of electrical charge through the heavy-metal strip. A method for switching a magnetization state of a nanomagnet is also described.

Abstract: A heterogeneous power distribution system for an integrated circuit includes a power network-on-chip that receives electrical power from one or more off-chip power converters. The power network-on-chip includes a mesh of power routers to power a plurality of on-chip loads. The mesh of power routers includes a plurality of integrated simple routers and a plurality of integrated complex power routers. Each complex power router of the plurality of complex power routers includes a microcontroller which is communicatively coupled to one or more switches and one or more sensors of the complex power router. The microcontroller is configured to run a process algorithm that dynamically routes and controls power according to a power delivery policy by controlling the one or more switches based on information received from the one or more sensors. A method to determine a near optimal distribution of power supply resources in a heterogeneous power delivery system is also described.

Abstract: A heterogeneous power distribution system for an integrated circuit includes a power network-on-chip that receives electrical power from one or more off-chip power converters. The power network-on-chip includes a mesh of power routers to power a plurality of on-chip loads. The mesh of power routers includes a plurality of integrated simple routers and a plurality of integrated complex power routers. Each complex power router of the plurality of complex power routers includes a microcontroller which is communicatively coupled to one or more switches and one or more sensors of the complex power router. The microcontroller is configured to run a process algorithm that dynamically routes and controls power according to a power delivery policy by controlling the one or more switches based on information received from the one or more sensors. A method to determine a near optimal distribution of power supply resources in a heterogeneous power delivery system is also described.

Abstract: The present invention provides a digitally controlled, current starved, pulse width modulator (PWM). In the PWM of the present invention, the amount of current from the voltage source to the ring oscillator is controlled by the proposed header circuit. By changing the header current, the pulse width of the switching signal generated at the output of the ring oscillator is dynamically controlled, where the duty cycle can vary between 50% and 90%. A duty cycle to voltage converter is used to ensure the accuracy of the system under process, voltage, and temperature (PVT) variations. The proposed pulse width modulator is appropriate for dynamic voltage scaling systems due to the small on-chip area and high accuracy under process, voltage, and temperature variations.

Abstract: A method for modifying a logic circuit layout to optimize circuit propagation delays for improved circuit operation is presented. The layout includes multiple logic gates connected by conductive segments. An initial layout of a physical electronic logic circuit having the plurality of logic gates is input. A respective size is determined for each of the logic gates in accordance with the initial layout and a circuit propagation delay criterion. The circuit propagation delay criterion is a joint function of properties of at least some of the logic gates and at least some of the conductive segments. A modified logic circuit layout is output. The modified logic circuit layout includes a layout of the logic gates arranged in accordance with the initial layout, where each of the logic gates is modified according to the respective determined size, thereby to obtain a modification of the logic circuit layout incorporating an optimized circuit propagation delay.

Abstract: A computer system for simulating performance of transmission lines, such as on-chip interconnects. The simulation uses direct extraction of poles, in contrast to conventional methods using poles obtained by a truncated transfer function. Using the directly extracted poles, far end response characteristic(s) can be determined to thereby aid in design of circuits using transmission lines. The far end response characteristic(s) that may be determined based on the directly extracted poles include, but are not necessarily limited to, frequency dependent effects, step response, ramp response, delay, 50% delay, rise time, 10% to 90% rise time, overshoot and normalized overshoot. A CAE tool designer and/or CAE tool user may decide how many pole pairs to directly extract to achieve a desired balance between computation resources required and resulting precision in the determination of far end response characteristic(s).

Abstract: The maximum effective radii of an on-chip decoupling capacitor based on a target impedance (discharge) and charge time are determined. To be effective, an on-chip decoupling capacitor should be placed such that both the power supply and the current load are located inside the appropriate effective radius. If this allocation is not feasible, the current load is partitioned into several circuit blocks, reducing and distributing the localized current demands. The on-chip decoupling capacitors are allocated to each block while satisfying both effective radii criteria.

Abstract: A system-on-chip or other circuit has an on-chip noise-free ground which is added to divert ground noise from the sensitive nodes. An on-chip decoupling capacitor, tuned in resonance with the parasitic inductance of the interconnects, can be provided to add an additional low impedance ground path.

Abstract: A method for modifying a logic circuit layout to optimize circuit propagation delays for improved circuit operation is presented. The layout includes multiple logic gates connected by conductive segments. An initial layout of a physical electronic logic circuit having the plurality of logic gates is input. A respective size is determined for each of the logic gates in accordance with the initial layout and a circuit propagation delay criterion. The circuit propagation delay criterion is a joint function of properties of at least some of the logic gates and at least some of the conductive segments. A modified logic circuit layout is output. The modified logic circuit layout includes a layout of the logic gates arranged in accordance with the initial layout, where each of the logic gates is modified according to the respective determined size, thereby to obtain a modification of the logic circuit layout incorporating an optimized circuit propagation delay.

Abstract: A variable threshold voltage keeper circuit technique is proposed for simultaneous power reduction and speed enhancement of domino logic circuits. The threshold voltage of the keeper transistor is dynamically modified during circuit operation to reduce the contention current without sacrificing noise immunity. The threshold voltage of the keeper transistor is controlled by a body bias generator which switches between two voltages in accordance with the clock signal.

Abstract: A variable threshold voltage keeper circuit technique is proposed for simultaneous power reduction and speed enhancement of domino logic circuits. The threshold voltage of the keeper transistor is dynamically modified during circuit operation to reduce the contention current without sacrificing noise immunity. The threshold voltage of the keeper transistor is controlled by a body bias generator which switches between two voltages in accordance with the clock signal.

Abstract: An ultra-low voltage rail-to-rail operational transconductance amplifier (OTA) is based on a standard digital 0.18 ?m CMOS process. Techniques for designing a 0.8 volt fully differential OTA include bias and reference current generator circuits. To achieve rail-to-rail operation, complementary input differential pairs are used, where the bulk-driven technique is applied to reduce the threshold limitation of the MOSFET transistors. The OTA gain is increased by using auxiliary gain boosting amplifiers.

Abstract: A domino logic circuit is configured to reduce power consumption. In a first embodiment, a sleep switch grounds the dynamic node during sleep mode. In a second embodiment, a low-swing circuit at the output reduces the output and keeper transistor gate voltage swings. A third embodiment combines those two techniques.

Abstract: A domino logic circuit is configured to reduce power consumption. In a first embodiment, a sleep switch grounds the dynamic node during sleep mode. In a second embodiment, a low-swing circuit at the output reduces the output and keeper transistor gate voltage swings. A third embodiment combines those two techniques.