Abstract: A system for transmitting signals via serial links includes a plurality of lanes for combining data onto a transmission media, a skew detector configured to detect skew among two of the plurality of lanes, and a variable delay circuit controlled by the skew detector, configured to delay the start of a clock signal to circuitry of one of the plurality of lanes.

Abstract: The present invention facilitates optical modulation skew adjustment. Components of an on chip optical device driver system can cooperatively operate to provide modulated driver signals to drive configuration of optical signals. A serializer is configured to receive parallel data signals and forward corresponding serial data signals. A multiplexing component is configured to selectively output an in-phase component and a quadrature component of the serial data signals, including implementing skew adjustments to aspects of a first output signal and a second output signal. An output stage is configured to output signals that modulate an optical signal, including the first output signal and the second output signal. An on chip skew detector is configured to detect a skew difference between the first output signal and the second output signal. A skew calibration component is configured to direct skew adjustment between the first output signal and the second output signal.

Abstract: The present invention facilitates optical modulation skew adjustment. Components of an on chip optical device driver system can cooperatively operate to provide modulated driver signals to drive configuration of optical signals. A serializer is configured to receive parallel data signals and forward corresponding serial data signals. A multiplexing component is configured to selectively output an in-phase component and a quadrature component of the serial data signals, including implementing skew adjustments to aspects of a first output signal and a second output signal. An output stage is configured to output signals that modulate an optical signal, including the first output signal and the second output signal. An on chip skew detector is configured to detect a skew difference between the first output signal and the second output signal. A skew calibration component is configured to direct skew adjustment between the first output signal and the second output signal.

Abstract: Various aspects provide for a digitally programmable analog duty-cycle correction circuit. For example, a system includes a duty-cycle correction circuit and a duty-cycle distortion detector circuit. The duty-cycle correction circuit adjusts a clock associated with the transmitter. The duty-cycle distortion detector circuit facilitates digital control of a duty-cycle of the clock associated with the duty-cycle correction circuit based on duty-cycle distortion error associated with output of the transmitter.

Abstract: A system for calibration of a multi-channel transceiver includes a plurality of voltage regulator circuits, wherein each circuit is configured to produce a voltage for circuitry of one channel of a multi-channel transceiver. The system also includes an analog multiplexer circuit configured to selectively route the output of one of the plurality of voltage regulator circuits to a single comparison circuit. The single comparison circuit is configured to compare an output of one of the plurality of voltage regulator circuits to a target reference voltage and produce an error signal representing a difference between the output of one of the plurality of voltage regulators and the target reference voltage. The system further includes a processor configured to accept the error signal and produce a feedback signal for the one of the plurality of voltage regulator circuits. The feedback signal is operable to adjust the voltage to minimize the difference.

Abstract: A system for transmitting signals via serial links includes a plurality of lanes for combining data onto a transmission media, a skew detector configured to detect skew among two of the plurality of lanes, and a variable delay circuit controlled by the skew detector, configured to delay the start of a clock signal to circuitry of one of the plurality of lanes.

Abstract: Various aspects provide for a digitally programmable analog duty-cycle correction circuit. For example, a system includes a duty-cycle correction circuit and a duty-cycle distortion detector circuit. The duty-cycle correction circuit adjusts a clock associated with the transmitter. The duty-cycle distortion detector circuit facilitates digital control of a duty-cycle of the clock associated with the duty-cycle correction circuit based on duty-cycle distortion error associated with output of the transmitter.

Abstract: Various aspects provide for error detection and compensation for a multiplexing transmitter. For example, a system can include an error detector circuit and a duty cycle correction circuit. The error detector circuit is configured to measure duty cycle error for a clock associated with a transmitter to generate error detector output based on a clock pattern for output generated by the transmitter in response to a defined bit pattern. The duty cycle correction circuit is configured to adjust the clock associated with the transmitter based on the error detector output. Additionally or alternatively, the error detector circuit is configured to measure quadrature error between an in-phase clock and a quadrature clock in response to the defined bit pattern. Additionally or alternatively, the system can include a quadrature error correction circuit configured to adjust phase shift between the in-phase clock and the quadrature clock based on quadrature error.

Abstract: Various aspects provide for error detection and compensation for a multiplexing transmitter. For example, a system can include an error detector circuit and a duty cycle correction circuit. The error detector circuit is configured to measure duty cycle error for a clock associated with a transmitter to generate error detector output based on a clock pattern for output generated by the transmitter in response to a defined bit pattern. The duty cycle correction circuit is configured to adjust the clock associated with the transmitter based on the error detector output. Additionally or alternatively, the error detector circuit is configured to measure quadrature error between an in-phase clock and a quadrature clock in response to the defined bit pattern. Additionally or alternatively, the system can include a quadrature error correction circuit configured to adjust phase shift between the in-phase clock and the quadrature clock based on quadrature error.

Abstract: The present invention facilitates optical modulation skew adjustment. Components of an on chip optical device driver system can cooperatively operate to provide modulated driver signals to drive configuration of optical signals. A serializer is configured to receive parallel data signals and forward corresponding serial data signals. A multiplexing component is configured to selectively output an in-phase component and a quadrature component of the serial data signals, including implementing skew adjustments to aspects of a first output signal and a second output signal. An output stage is configured to output signals that modulate an optical signal, including the first output signal and the second output signal. An on chip skew detector is configured to detect a skew difference between the first output signal and the second output signal. A skew calibration component is configured to direct skew adjustment between the first output signal and the second output signal.

Abstract: Various aspects provide for a multiplexer for high-speed serial links. For example, a system can include a first stage data path multiplexer circuit and a second stage data path multiplexer circuit. The first stage data path multiplexer circuit comprises a first inverter circuit to select a first data signal from a set of data signals and a second inverter circuit to select a second data signal from the set of data signals. The first inverter circuit comprises a first set of inverters and a first set of transmission gates. The second inverter circuit comprises a second set of inverters and a second set of transmission gates. The second stage data path multiplexer circuit is configured as a third inverter circuit to select the first data signal or the second data signal as an output data signal. The third inverter circuit comprises a third set of inverters and a third set of transmission gates.

Abstract: Various aspects provide for error detection and compensation for a multiplexing transmitter. For example, a system can include an error detector circuit and a duty cycle correction circuit. The error detector circuit is configured to measure duty cycle error for a clock associated with a transmitter to generate error detector output based on a clock pattern for output generated by the transmitter in response to a defined bit pattern. The duty cycle correction circuit is configured to adjust the clock associated with the transmitter based on the error detector output. Additionally or alternatively, the error detector circuit is configured to measure quadrature error between an in-phase clock and a quadrature clock in response to the defined bit pattern. Additionally or alternatively, the system can include a quadrature error correction circuit configured to adjust phase shift between the in-phase clock and the quadrature clock based on quadrature error.

Abstract: A voltage regulator operable to selectively supply an extended range of regulated voltages by using multiple levels of unregulated voltages and a single amplifier. The voltage regulator is coupled to a plurality of passing elements in parallel via enabling switches. Each passing element is configured to receive a respective level of unregulated voltage and, when enabled, can pass current to the voltage regulator and thereby induce a corresponding level of regulated voltage at the output terminal of the voltage regulator. To output a specific regulated voltage, the voltage regulator can operate in a single passing mode in which only the passing element receiving the corresponding unregulated voltage is enabled to pass current. Alternatively, in a parallel passing mode, two or more passing elements receiving different levels of unregulated voltages can be enabled to pass current.

Abstract: Various aspects provide for a multiplexer for high-speed serial links. For example, a system can include a first stage data path multiplexer circuit and a second stage data path multiplexer circuit. The first stage data path multiplexer circuit comprises a first inverter circuit to select a first data signal from a set of data signals and a second inverter circuit to select a second data signal from the set of data signals. The first inverter circuit comprises a first set of inverters and a first set of transmission gates. The second inverter circuit comprises a second set of inverters and a second set of transmission gates. The second stage data path multiplexer circuit is configured as a third inverter circuit to select the first data signal or the second data signal as an output data signal. The third inverter circuit comprises a third set of inverters and a third set of transmission gates.

Abstract: A voltage regulator operable to selectively supply an extended range of regulated voltages by using multiple levels of unregulated voltages and a single amplifier. The voltage regulator is coupled to a plurality of passing elements in parallel via enabling switches. Each passing element is configured to receive a respective level of unregulated voltage and, when enabled, can pass current to the voltage regulator and thereby induce a corresponding level of regulated voltage at the output terminal of the voltage regulator. To output a specific regulated voltage, the voltage regulator can operate in a single passing mode in which only the passing element receiving the corresponding unregulated voltage is enabled to pass current. Alternatively, in a parallel passing mode, two or more passing elements receiving different levels of unregulated voltages can be enabled to pass current.

Abstract: An analog-based architecture is used to produce tap spacings in an n-tap UI-spaced equalizer without the need for digital clock-driven elements. The analog voltage-controlled delay cell circuits control the amount of applied delay based on the measured phase difference between quarter-rate clock signals. Because low speed clock signals are sufficient for comparison purposes, the analog delay cells can be placed before the quarter-rate multiplexors in the data path. The use of analog-based delay cells eliminates the need to route high-speed clock signals to multiple digital delay elements that are typically used to achieve UI-spaced data signals in n-tap FIR equalizers. Timing margin issues can also be eliminated since digital clocked elements are not used to produce the UI spaced delays. The analog-based delay approach also consumes less power relative equalizers that use multiple digital delay elements requiring high speed clock signals.

Abstract: An analog-based architecture is used to produce tap spacings in an n-tap UI-spaced equalizer without the need for digital clock-driven elements. The analog voltage-controlled delay cell circuits control the amount of applied delay based on the measured phase difference between quarter-rate clock signals. Because low speed clock signals are sufficient for comparison purposes, the analog delay cells can be placed before the quarter-rate multiplexors in the data path. The use of analog-based delay cells eliminates the need to route high-speed clock signals to multiple digital delay elements that are typically used to achieve UI-spaced data signals in n-tap FIR equalizers. Timing margin issues can also be eliminated since digital clocked elements are not used to produce the UI spaced delays. The analog-based delay approach also consumes less power relative equalizers that use multiple digital delay elements requiring high speed clock signals.

Abstract: An analog-based architecture is used to produce tap spacings in an n-tap fractionally-spaced equalizer without the need for digital clock-driven elements. The analog voltage-controlled delay cell circuits control the amount of applied delay based on the measured phase difference between quarter-rate clock signals. Because low speed clock signals are sufficient for comparison purposes, the analog delay cells can be placed before the quarter-rate multiplexors in the data path. The use of analog-based delay cells eliminates the need to route high-speed clock signals to multiple digital delay elements that are typically used to achieve fractionally spaced data signals in n-tap FIR equalizers. Timing margin issues can also be eliminated since digital clocked elements are not used to produce the fractionally spaced delays. The analog-based delay approach also consumes less power relative equalizers that use multiple digital delay elements requiring high speed clock signals.

Abstract: According to general aspects, embodiments of the invention provide an analog front end (AFE) capable of combining two independent 106 MHz G.fast baseband transmission channels into a single 212 MHz wide G.fast transmission channel. In these and other embodiments, an AFE according to the invention is also capable of interfacing to a single 212 MHz G.fast transmission channels as well as a single 106 MHz G.fast transmission channel.

Abstract: Peak-to-average ratio reduction is achieved by detecting peaks in an original analog signal that exceed a given threshold. Segments of the original analog signal containing such peaks are treated (e.g., by attenuation) and a composite analog signal is assembled that includes treated and untreated segments of the original analog signal. The composite analog signal is processed to perform analog-to-digital conversion to generate a composite digital signal. Segments of the composite digital signal corresponding to the treated segments of the original analog signal are reverse-treated or otherwise treated again to undo treatment of the segments of the original analog signal. A final output digital signal is generated that corresponds to the original analog signal in digital form.