Abstract: A display device includes pixels arranged in columns and rows, in which the pixels of a row can be selected by means of a row voltage supplied via control lines, and column voltages that correspond to the image data of the selected pixel to be displayed can be supplied via data lines, wherein mutually adjoining pixel groups arranged in a row or column, consisting of adjoining pixels of a row or column, are connected to adjoining control lines or data lines, as applicable, in alternation.

Abstract: The present invention provides a driving circuit capable of reducing power consumption in an amplifier for outputting a target voltage. A driving circuit for driving a capacitive load Ccol of a display device, comprising: driving signal supplying means (10) for supplying a driving signal Vin having a target voltage to be applied; an amplifying stage (20) for receiving the driving signal Vin and selectively outputting the driving signal Vin to the capacitive load Ccol; and a pair of current sources Ipcp, Ipcn for selectively supplying a positive current and a negative current to the capacitive load Ccol, respectively during their on-states. The driving circuit repeats a repetitive operation including a pre-operation where any one of the current sources Ipcp, Ipcn is switched ON in accordance with the driving signal Vin and then switched OFF and a post-operation where the amplifying stage (20) is switched to a state for outputting the driving signal Vin to the capacitive load Ccol after the pre-operation.

Abstract: The invention relates to a display device (2) with pixels (8) arranged in columns m and rows n, wherein the pixels of a row n can be selected by a row voltage (VROW) supplied through control lines (6), and column voltages (VCOL) that correspond to the picture data of the selected pixels to be displayed can be supplied through data lines (7). The invention further relates to a method of controlling such a display device. To obtain a display device in which an optimized picture quality is achieved in combination with a long battery life and low manufacturing costs, it is proposed to connect the mutually adjoining pixel groups arranged in one row or column, said groups comprising adjoining pixels of one row or column, to adjoining control lines (6n, 6n+1) or data lines (7m, 7m+1) in alternation. This renders it possible to control such a display device by a conventional control method.

Abstract: In order to preclude unauthorized access to a memory, for example after testing, two EEPROM cells are programmed and their outputs are subjected to a logic operation, the result being stored in a memory element and being evaluated. The cells are arranged in such a manner that they are programmed together in anti-parallel. A well-defined initial condition before a test is established by changing the control gate voltage, which causes both cells to be set to an initial state with similar output signals. The initial state is stored in the storage element and is evaluated. It is not until the initial condition has been established that the EEPROM cells are programmed and the correct programming is tested. Locking is effected by means of a single programming pulse and is irreversible.

Abstract: Text Integrated circuit device (20) comprising a silicon substrate (21), integrated devices (22) with contacts (23.1, 23.2), an isolating layer (24) at least partially covering the integrated devices (22) and comprising conducting areas (24.1, 24.2) which establish a conductive path to the contacts (23.1, 23.2) of the integrated devices (22). A metallization level (25) with metal lines (26.1, 26.2, 26.3, 26.4) is provided which connect to one of the contacts (23.2). The metal lines (26.1, 26.2, 26.3, 26.4) are situated above the isolating layer (24). A passivation layer (27)—situated above the metallization level (25)—comprises at least two contact areas (28.1, 28.2) for partially exposing at least two of the metal lines (26.2, 26.4). A bump bridge (29) comprising a conductive, low-resistance material, is situated on the passivation layer (27). The bump bridge (29) has a high aspect ratio and provides for a conductive connection between at least two of the metal lines (26.2, 26.4).

Abstract: In order to preclude unauthorized access to a memory, for example after testing, two EEPROM cells are programmed and their outputs are subjected to a logic operation, the result being stored in a memory element and being evaluated. The cells are arranged in such a manner that they are programmed together in anti-parallel. A well-defined initial condition before a test is established by changing the control gate voltage, which causes both cells to be set to an initial state with similar output signals. The initial state is stored in the storage element and is evaluated. It is not until the initial condition has been established that the EEPROM cells are programmed and the correct programming is tested.

Abstract: A voltage converter, for converting an input voltage (U.sub.i) to an output voltage (U.sub.0), includes a plurality of cascaded voltage multipliers (VM1-VMN) having clock inputs, a control circuit (CNTRLG) for supplying clock signals to the clock inputs, for controlling the voltage multipliers (VM1-VMN). The control circuit (CNTRLG) includes circuitry (SL) for activating selected ones from the plurality of the voltage multipliers (VM1-VMN). The clock signals can be programmed to a part of the voltage multiplier to a non-active state. The voltage converter can, in addition, be provided with monitoring circuitry (MN) coupled between the output of the voltage converter and an input of the circuitry (SL). The monitoring means (MN) measures the output voltage (U.sub.0) in order to take a decision about the required number N of active voltage multipliers (VM1-VMN).