Abstract: A circuit assembly includes a printed circuit board (PCB), and a power management arrangement positioned on and electrically coupled to the PCB. The power management arrangement includes a substrate, a power management circuit chip positioned on and electrically coupled to the substrate, and a shield can positioned over the substrate and providing electromagnetic shielding for the power management chip. The circuit assembly further includes a self-shielded coil positioned on and electrically coupled to the PCB, wherein the self-shielded coil is positioned adjacent to the power management arrangement.

Abstract: A circuit assembly includes a printed circuit board (PCB), and a power management arrangement positioned on and electrically coupled to the PCB. The power management arrangement includes a substrate, a power management circuit chip positioned on and electrically coupled to the substrate, and a shield can positioned over the substrate and providing electromagnetic shielding for the power management chip. The circuit assembly further includes a self-shielded coil positioned on and electrically coupled to the PCB, wherein the self-shielded coil is positioned adjacent to the power management arrangement.

Abstract: The invention describes a method for adjusting signal propagation times in a memory system in which a controller is connected to at least one memory chip via a plurality of connecting lines for the purpose of transmitting control and data signals and at least one time reference signal. In line with the invention, the propagation time differences between connecting lines are ascertained from the result of echo measurements. To this end a respective transmitted pulse is applied to one end, selected as the transmission end, of the connecting lines in question, while the other end of the connecting lines in question is respectively terminated with a reflective termination. At the transmission end, the echo time which elapses between one edge of the transmitted pulse and the appearance of this edge's echo reflected from the other end is measured. On the basis of the ascertained propagation time differences, regulatable delay devices are set in order to compensate for these propagation time differences.

Abstract: Methods and apparatus for setting various terminations of a memory chip. The memory chip includes a terminal, a termination circuit that can be connected to the terminal in order to terminate the terminal with a settable resistance value, a control command port for receiving a control command signal, and a control circuit that is connected to the termination circuit in order to set a resistance value as a function of a received control command signal.

Abstract: A method is provided for adapting the phase relationship between a clock signal and a strobe signal for accepting write data to be transmitted into a memory circuit, a write command signal being transmitted to the memory circuit in a manner synchronized with the clock signal, a write data signal being transmitted synchronously with the strobe signal, a phase offset between the transmitted clock signal and the transmitted strobe signal being set such that the write data are reliably accepted in the memory circuit.

Abstract: Methods and apparatus for setting various terminations of a memory chip. In one embodiment, the memory chip includes a terminal, a termination circuit that can be connected to the terminal in order to terminate the terminal with a settable resistance value, a control command port for receiving a control command signal, and a control circuit that is connected to the termination circuit in order to set a resistance value as a function of a received control command signal.

Abstract: A method is provided for adapting the phase relationship between a clock signal and a strobe signal for accepting write data to be transmitted into a memory circuit, a write command signal being transmitted to the memory circuit in a manner synchronized with the clock signal, a write data signal being transmitted synchronously with the strobe signal, a phase offset between the transmitted clock signal and the transmitted strobe signal being set such that the write data are reliably accepted in the memory circuit.

Abstract: The invention describes a method for adjusting signal propagation times in a memory system in which a controller is connected to at least one memory chip via a plurality of connecting lines for the purpose of transmitting control and data signals and at least one time reference signal. In line with the invention, the propagation time differences between connecting lines are ascertained from the result of echo measurements. To this end a respective transmitted pulse is applied to one end, selected as the transmission end, of the connecting lines in question, while the other end of the connecting lines in question is respectively terminated with a reflective termination. At the transmission end, the echo time which elapses between one edge of the transmitted pulse and the appearance of this edge's echo reflected from the other end is measured. On the basis of the ascertained propagation time differences, regulatable delay devices are set in order to compensate for these propagation time differences.

Abstract: A psuedostatic memory circuit is selected by a memory selection signal. A control circuit, in a first operating mode, carries out a refresh of the memory area at a refresh address after reception of the refresh request signal by generation of a refresh signal if the memory circuit is deselected or if, in the event of selection of the memory circuit by the memory selection signal, the access to the memory area is ended before the generation of a further refresh request signal. The control circuit, in a second operating mode, interrupts an access to the memory area for the writing and read-out of data and carries out a refresh of the memory area by generation of a refresh signal if the memory circuit is selected and a further refresh request signal is received before the ending of the access to the memory area.

Abstract: An integrated circuit has a synchronous circuit and an asynchronous circuit. A clock-controlled input register circuit and an output register circuit for storing data are each connected to the synchronous circuit and the asynchronous circuit. Data are transferred from the synchronous circuit into the input register circuit, from where they are transferred into the asynchronous circuit and processed in the asynchronous circuit. Processed data are transferred into the output register circuit. A sequence controller generates a respective control clock signal for the register circuits in a manner dependent on the data processing duration of the asynchronous circuit. This enables a high data throughput between the synchronous circuit and the asynchronous circuit independently of a clock frequency of the synchronous circuit.

Abstract: A semiconductor memory apparatus includes a memory cell array having a multiplicity of data lines and a multiplicity of local amplifiers, each of the local amplifiers being associated with a data line. An amplifier group includes at least two amplifiers selected from the multiplicity of local amplifiers. Each amplifier has at least a pair of selection transistors for selecting a particular amplifier from the amplifier group. The selection transistors have a common gate, an unshared intrinsic diffusion region, and a shared intrinsic diffusion region, the shared intrinsic diffusion region being shared with an adjacent selection transistor from an adjacent amplifier.

Abstract: An electronic circuit for generating an output voltage has a defined temperature dependence, a bandgap circuit for generating a defined temperature-constant voltage and a temperature-dependent current with a defined temperature dependence, and a conversion circuit for generating the output voltage from the temperature-dependent current and the temperature-constant voltage. The conversion circuit has a first resistor at whose first terminal the temperature-constant voltage is applied, and whose second terminal is connected to a first terminal of a second resistor. The second terminal of the second resistor is connected to a supply voltage potential, and a first terminal of a third resistor is connected to the second terminal of the first resistor. The temperature-dependent current is supplied to a second terminal of the third resistor, and it being possible to tap the output voltage at the second terminal of the third resistor.

Abstract: The electrical circuit includes a plurality of circuit components which are connected via a bus. At least one of the circuit components can be tested independently of the other circuit components. The circuit component which is to be tested and the method for testing the circuit component are distinguished in that steps are taken to ensure that, during testing, the circuit component which is tested, outputs no data to the bus, and/or instead of the data which would need to be output to the bus during normal operation, outputs other data to the bus.

Abstract: An electronic circuit for generating an output voltage has a defined temperature dependence, a bandgap circuit for generating a defined temperature-constant voltage and a temperature-dependent current with a defined temperature dependence, and a conversion circuit for generating the output voltage from the temperature-dependent current and the temperature-constant voltage. The conversion circuit has a first resistor at whose first terminal the temperature-constant voltage is applied, and whose second terminal is connected to a first terminal of a second resistor. The second terminal of the second resistor is connected to a supply voltage potential, and a first terminal of a third resistor is connected to the second terminal of the first resistor. The temperature-dependent current is impressed at a second terminal of the third resistor, and it being possible to tap the output voltage at the second terminal of the third resistor.