Patents by Inventor Eckhard Brass
Eckhard Brass has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7307869Abstract: A method for reading data from a dynamic memory circuit is provided, wherein at least one memory cell can be addressed via a word line and a bit line, wherein the memory cell is connected to a first reading amplifier via the bit line, and wherein a switching element, which in the off state isolates the first reading amplifier from the bit line, is provided. The method comprises: a) turning on the switching element to connect the first reading amplifier to the bit line, b) activating the word line to activate the memory cell for reading, c) activating the first reading amplifier to initiate assessment of the information on the bit line, d) turning off the switching element to isolate the first reading amplifier from the bit line, and e) transferring the information which has been read to a data bus.Type: GrantFiled: December 2, 2005Date of Patent: December 11, 2007Assignee: Infineon Technologies AGInventors: Bernd Klehn, Hermann Fischer, Eckhard Brass, Ralf Klein, Thomas Schumann
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Publication number: 20060146593Abstract: A method for reading data from a dynamic memory circuit is provided, wherein at least one memory cell can be addressed via a word line and a bit line, wherein the memory cell is connected to a first reading amplifier via the bit line, and wherein a switching element, which in the off state isolates the first reading amplifier from the bit line, is provided. The method comprises: a) turning on the switching element to connect the first reading amplifier to the bit line, b) activating the word line to activate the memory cell for reading, c) activating the first reading amplifier to initiate assessment of the information on the bit line, d) turning off the switching element to isolate the first reading amplifier from the bit line, and e) transferring the information which has been read to a data bus.Type: ApplicationFiled: December 2, 2005Publication date: July 6, 2006Inventors: Bernd Klehn, Hermann Fischer, Eckhard Brass, Ralf Klein, Thomas Schumann
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Patent number: 6972549Abstract: A bandgap reference circuit is provided in which the conventional current loop with a current mirror for feeding a differential amplifier is replaced by a reference current that flows through a resistor connected to the bias input of the differential amplifier. In conjunction with a simpler construction and suitability for lower supply voltages, the circuit exhibits an improved supply voltage rejection PSRR over the prior art.Type: GrantFiled: January 24, 2005Date of Patent: December 6, 2005Assignee: Infineon Technologies AGInventors: Eckhard Brass, Christian Grewing, Jürgen Oehm
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Patent number: 6970395Abstract: A memory device includes a delay-locked loop circuit having delay elements and a synchronization circuit coupled to the delay-locked loop circuit. The synchronization circuit receives a synchronization enable signal and outputs a plurality of enable signals, including an enable signal coupled to an output circuit. Because the enable signal is synchronized with the read signal, it is possible to provide more time to read data into the buffer. A method of reading data from a memory device couples a synchronization enable signal and an external clock signal to a synchronization circuit. A read signal and an output enable are generated based upon a synchronization enable signal and a delayed clock signal of the external clock signal. Because the output signal is synchronized to the read signal, more time is allowed for the sense function.Type: GrantFiled: September 8, 2003Date of Patent: November 29, 2005Assignee: Infineon Technologies AGInventors: Thoai-Thai Le, Ralf Klein, Eckhard Brass, George Alexander
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Publication number: 20050184718Abstract: A bandgap reference circuit is provided in which the conventional current loop with a current mirror for feeding a differential amplifier is replaced by a reference current that flows through a resistor connected to the bias input of the differential amplifier. In conjunction with a simpler construction and suitability for lower supply voltages, the circuit exhibits an improved supply voltage rejection PSRR over the prior art.Type: ApplicationFiled: January 24, 2005Publication date: August 25, 2005Inventors: Eckhard Brass, Christian Grewing, Jurgen Oehm
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Patent number: 6880055Abstract: So that semiconductor memory devices can be used optimally with regard to different possible operating frequencies, according to the invention, a register area is formed in which frequency information with regard to a present operating frequency can be stored in coded form and be retrieved for a configuration and adaptation of the semiconductor memory device.Type: GrantFiled: September 30, 2002Date of Patent: April 12, 2005Assignee: Infineon Technologies AGInventors: Eckhard Brass, Kazimierz Szczypinski
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Publication number: 20050052943Abstract: The present invention relates to a memory device which enables a greater amount of time to read data into a buffer. In particular, a memory device according to one aspect of the present invention comprises a delay-locked loop circuit having a plurality of delay elements and a synchronization circuit coupled to the delay-locked loop circuit. The synchronization circuit also receives a synchronization enable signal and outputs a plurality of enable signals, including an enable signal coupled to an output circuit. Because the enable signal coupled to the output circuit is synchronized with the read signal, it is possible to provide more time to read data into the buffer. According to another aspect of the present invention, a method of reading data from a memory device couples a synchronization enable signal to a synchronization circuit. An external clock signal is also coupled to a delay-locked loop circuit.Type: ApplicationFiled: September 8, 2003Publication date: March 10, 2005Inventors: Thoai-Thai Le, Ralf Klein, Eckhard Brass, George Alexander
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Patent number: 6838917Abstract: A circuit configuration for processing data, particularly a semiconductor memory chip, has a control circuit for setting a phase or frequency relationship between two signals. A digital counter detects a phase or frequency difference between the two signals, and the counter reading is used for regulating the phase or frequency relationship. Trials have shown that the counter reading indicates an operating state in the circuit configuration and therefore represents a simple signal for assessing the operating state of the circuit configuration. Preferably, the counter reading is taken as a basis for adjusting the speed or power of time-critical or performance-critical circuit parts in the circuit configuration so that an operating state with an intermediate switching speed is obtained.Type: GrantFiled: October 7, 2002Date of Patent: January 4, 2005Assignee: Infineon Technologies AGInventors: Eckhard Brass, Bernd Klehn, Ralf Klein, Thoai-Thai Le
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Publication number: 20030067334Abstract: A circuit configuration for processing data, particularly a semiconductor memory chip, has a control circuit for setting a phase or frequency relationship between two signals. A digital counter detects a phase or frequency difference between the two signals, and the counter reading is used for regulating the phase or frequency relationship. Trials have shown that the counter reading indicates an operating state in the circuit configuration and therefore represents a simple signal for assessing the operating state of the circuit configuration. Preferably, the counter reading is taken as a basis for adjusting the speed or power of time-critical or performance-critical circuit parts in the circuit configuration so that an operating state with an intermediate switching speed is obtained.Type: ApplicationFiled: October 7, 2002Publication date: April 10, 2003Inventors: Eckhard Brass, Bernd Klehn, Ralf Klein, Thoai-Thai Le
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Publication number: 20030062547Abstract: So that semiconductor memory devices can be used optimally with regard to different possible operating frequencies, according to the invention, a register area is formed in which frequency information with regard to a present operating frequency can be stored in coded form and be retrieved for a configuration and adaptation of the semiconductor memory device.Type: ApplicationFiled: September 30, 2002Publication date: April 3, 2003Inventors: Eckhard Brass, Kazimierz Szczypinski
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Patent number: 6456553Abstract: A circuit configuration for switching over a receiver circuit, in particular in DRAM memories, between a standby mode and an operating mode, includes a differential amplifier functioning as a receiver receiving a control voltage derived from a reference current and generated or fed in for setting a correct operating point of said differential amplifier. A line feeds a current for generating the control voltage. Switching elements are disposed in said line for each receiver. The switching elements are permanently closed in the operating mode by an enable signal present at said switching elements for continuously supplying the current for generating the control voltage. The switching elements are closed at discrete times or periodically in the standby mode by feeding a refresh signal for discontinuously refreshing the control voltage. A DRAM memory having the circuit configuration is also provided.Type: GrantFiled: July 3, 2001Date of Patent: September 24, 2002Assignee: Infineon Technologies AGInventors: Eckhard Brass, Thoai-Thai Le, Jürgen Lindolf, Joachim Schnabel
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Patent number: 6389086Abstract: A digital circuit has a signal input terminal and a signal output terminal. The digital circuit additionally has a logic circuit unit, whose input is connected to the signal input terminal and whose output is connected to the signal output terminal via a switching element. Furthermore, it has a filter unit, whose input is connected to the signal input terminal and whose output is connected to a control input of the switching element. The filter unit serves for suppressing glitches on a digital signal present at its input.Type: GrantFiled: March 8, 2000Date of Patent: May 14, 2002Assignee: Infineon Technologies AGInventors: Thoai-Thai Le, Eckhard Brass, Markus Biebl
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Publication number: 20020053944Abstract: A circuit configuration for switching over a receiver circuit, in particular in DRAM memories, between a standby mode and an operating mode, includes a differential amplifier functioning as a receiver receiving a control voltage derived from a reference current and generated or fed in for setting a correct operating point of said differential amplifier. A line feeds a current for generating the control voltage. Switching elements are disposed in said line for each receiver. The switching elements are permanently closed in the operating mode by an enable signal present at said switching elements for continuously supplying the current for generating the control voltage. The switching elements are closed at discrete times or periodically in the standby mode by feeding a refresh signal for discontinuously refreshing the control voltage. A DRAM memory having the circuit configuration is also provided.Type: ApplicationFiled: July 3, 2001Publication date: May 9, 2002Inventors: Eckhard Brass, Thoai-Thai Le, Jurgen Lindolf, Joachim Schnabel
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Patent number: 6370069Abstract: A method for testing a multiplicity of word lines of a semiconductor memory configuration in a multiple word line wafer test is described. To prevent a pulling-up of inactive word lines which are at a negative voltage when the active word lines are ramped down, the inactive word lines are decoupled from the negative word line voltage and are connected to a high impedance shortly before the active word lines are ramped down.Type: GrantFiled: May 29, 2001Date of Patent: April 9, 2002Assignee: Infineon Technologies AGInventors: Eckhard Brass, Thilo Schaffroth, Joachim Schnabel, Helmut Schneider
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Publication number: 20010048621Abstract: A method for testing a multiplicity of word lines of a semiconductor memory configuration in a multiple word line wafer test is described. To prevent a pulling-up of inactive word lines which are at a negative voltage when the active word lines are ramped down, the inactive word lines are decoupled from the negative word line voltage and are connected to a high impedance shortly before the active word lines are ramped down.Type: ApplicationFiled: May 29, 2001Publication date: December 6, 2001Inventors: Eckhard Brass, Thilo Schaffroth, Joachim Schnabel, Helmut Schneider
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Patent number: 6125073Abstract: In an integrated semiconductor memory having a memory cell array divided into memory banks, supply potentials with high drive capability are applied to the memory banks only if the respective memory bank is activated for access to a memory cell. For this purpose a supply voltage assigned to the respective memory bank is controlled by the same address signal as the memory bank. The supply voltage sources generate a word line potential, a bit line potential or a substrate potential. As a result, a power loss is reduced.Type: GrantFiled: September 8, 1999Date of Patent: September 26, 2000Assignee: Siemens AktiengesellschaftInventors: Thoai-Thai Le, Jurgen Lindolf, Eckhard Brass, Martin Brox