Abstract: Systems and methods for employing hardware-assisted virtualization for implementing a secure video output path. An example processing system comprises: a memory; a shared interconnect; and a processing core communicatively coupled to the memory via the shared interconnect, the processing core to: initialize a first virtual machine and a second virtual machine; responsive to receiving a memory access transaction initiated by the first virtual machine to access a memory buffer, tag the memory access transaction with an identifier of the first virtual machine; and responsive to receiving a digital content decoder access transaction initiated by the second virtual machine, tag the digital decoder access transaction with an identifier of the second virtual machine.

Abstract: Computing device with a processing system including a plurality of user sub-systems, a plurality of user sub-system identifiers respectively identifying one user sub-system of the plurality of user sub-systems, a processor configured to run the processing system, a cryptography unit configured to provide at least one cryptographic mechanism, a cryptography unit secret key assigned to the cryptography unit, and a binder configured to bind the cryptography unit secret key to the user sub-system identifier of a currently running user sub-system.

Abstract: Systems and methods for employing hardware-assisted virtualization for implementing a secure video output path. An example processing system comprises: a memory; a shared interconnect; and a processing core communicatively coupled to the memory via the shared interconnect, the processing core to: initialize a first virtual machine and a second virtual machine; responsive to receiving a memory access transaction initiated by the first virtual machine to access a memory buffer, tag the memory access transaction with an identifier of the first virtual machine; and responsive to receiving a digital content decoder access transaction initiated by the second virtual machine, tag the digital decoder access transaction with an identifier of the second virtual machine.

Abstract: A data processing system including a memory configured to store confidential data and non-confidential data; a cache memory which is configured to cache data stored in the memory and which comprises a first cache memory region and a second cache memory region; a processing circuit configured to carry out, in a first state of the data processing system, a cryptographic algorithm which operates on the confidential data and on the non-confidential data, wherein the confidential data are cached using the first cache memory region and the non-confidential data are cached using the second cache memory region; and an invalidating circuit configured to invalidate the first cache memory region when the data processing system switches from the first state into a second state.

Abstract: Processor arrangement having a first processor, a second processor, and at least one memory configured to be shared by the first processor and the second processor. The second processor has a memory interface configured to provide access to the at least one memory, and a processor communication interface configured to provide a memory access service to the first processor. The first processor has a processor communication interface configured to use the memory access service from the second processor. The first processor and the second processor use at least one cryptographic mechanism in the context of the memory access service.

Abstract: A first time indication which can be changed by a user and stored in a first memory. Furthermore, in the case of a change in the first time indication which is performed externally to the checking device, the difference between the stored first time indication and the changed first time indication is determined. Furthermore, it is checked whether a predetermined criterion is met by using a trustworthy second time indication, the first time indication and the difference.

Abstract: A data processing system including a memory configured to store confidential data and non-confidential data; a cache memory which is configured to cache data stored in the memory and which comprises a first cache memory region and a second cache memory region; a processing circuit configured to carry out, in a first state of the data processing system, a cryptographic algorithm which operates on the confidential data and on the non-confidential data, wherein the confidential data are cached using the first cache memory region and the non-confidential data are cached using the second cache memory region; and an invalidating circuit configured to invalidate the first cache memory region when the data processing system switches from the first state into a second state.

Abstract: Computing device with a processing system inclduing a plurality of user sub-systems, a plurality of user sub-system identifiers respectively identifying one user sub-system of the plurality of user sub-systems, a processor configured to run the processing system, a cryptography unit configured to provide at least one cryptographic mechanism, a cryptography unit secret key assigned to the cryptography unit, and a binder configured to bind the cryptography unit secret key to the user sub-system identifier of a currently running user sub-system.

Abstract: Processor arrangement having a first processor, a second processor, and at least one memory configured to be shared by the first processor and the second processor. The second processor has a memory interface configured to provide access to the at least one memory, and a processor communication interface configured to provide a memory access service to the first processor. The first processor has a processor communication interface configured to use the memory access service from the second processor. The first processor and the second processor use at least one cryptographic mechanism in the context of the memory access service.

Abstract: A method and device within a speech processing unit (SPU) for reducing scheduling delay between the SPU and a radio network node. Within the SPU, data packets are processed in a plurality of time slots that are subunits of frames. The device receives timing information from the node that identifies a beginning and an ending of processing periods in the node. The timing information is utilized to select a time slot within each frame as a target time slot. The target time slot has a position within each frame such that the scheduling delay between the ending of a processing period in the node and the beginning of the target time slot is minimized. Data packets for a particular channel are assigned to the target time slot to reduce the scheduling delay. The phase of the frame is then adjusted by erasing superfluous data packets.

Abstract: A first time indication which can be changed by a user and stored in a first memory. Furthermore, in the case of a change in the first time indication which is performed externally to the checking device, the difference between the stored first time indication and the changed first time indication is determined. Furthermore, it is checked whether a predetermined criterion is met by using a trustworthy second time indication, the first time indication and the difference.

Abstract: A data processing device having data input unit for inputting data, a first processor, and a second processor. The first processor is set up for receiving and processing data which are input into the data input unit in a first data input mode, and the second processor is set up for receiving and processing data which are input into the data input unit in a second, security-related data input mode.

Abstract: In the access method for a memory chip, particularly for a NAND flash memory chip, the memory access is dependent upon what type of memory chip is used. In this case, the method is intended to support various types of memory chip. According to the inventive method, data are first read from the memory chip which contain a memory-chip-typical information item for the access to the memory chip. The subsequent access to the memory chip is performed using the memory-chip-typical information item contained in the data.

Abstract: The invention provides method and apparatus for transporting tone signalling information through a GCME link in a GSM network supporting TFO and speech compression modes for the passage of signals through the link, respectively using TFO frames and TRAU-like In a data stream to the local entrance to the GCME link, a tone signal to be transported is detected. The detected tone signal is coded into bits of a TFO or TRAU-like frame for sending through the GCME link, including setting bits to mark the frame as a containing tone signalling information and setting bits to identify the detected tone signal, whereby the tone signalling information is transported in-band through the GCME link as a marked TFO or TRAU-like frame. At the remote exit from the GCME link, the marked frame is detected and the tone signal regenerated in dependence upon the bits of the marked frame.

Abstract: A method and device within a speech processing unit (SPU) for reducing scheduling delay between the SPU and a radio network node. Within the SPU, data packets are processed in a plurality of time slots that are subunits of frames. The device receives timing information from the node that identifies a beginning and an ending of processing periods in the node. The timing information is utilized to select a time slot within each frame as a target time slot. The target time slot has a position within each frame such that the scheduling delay between the ending of a processing period in the node and the beginning of the target time slot is minimized. Data packets for a particular channel are assigned to the target time slot to reduce the scheduling delay. The phase of the frame is then adjusted by erasing superfluous data packets.

Abstract: The invention provides method and apparatus for transporting tone signalling information through a GCME link in a GSM network supporting TFO and speech compression modes for the passage of signals through the link, respectively using TFO frames and TRAU-like In a data stream to the local entrance to the GCME link, a tone signal to be transported is detected. The detected tone signal is coded into bits of a TFO or TRAU-like frame for sending through the GCME link, including setting bits to mark the frame as a containing tone signalling information and setting bits to identify the detected tone signal, whereby the tone signalling information is transported in-band through the GCME link as a marked TFO or TRAU-like frame. At the remote exit from the GCME link, the marked frame is detected and the tone signal regenerated in dependence upon the bits of the marked frame.