Patents by Inventor Eckhard Ditzel

Eckhard Ditzel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10468569
    Abstract: A method of producing at least one connection carrier includes: A) providing a carrier plate with a planar top face; B) applying at least one electrically insulating insulation strip to the top face and cohesively connecting the carrier plate and the insulation strip; and C) applying at least one electrically conductive conductor strip to an adhesive surface of the insulation strip and cohesively connecting the insulation strip and the conductor strip, wherein the conductor strip and the carrier plate are electrically insulated from one another by the insulation strip.
    Type: Grant
    Filed: April 19, 2016
    Date of Patent: November 5, 2019
    Assignees: OSRAM Opto Semiconductor GmbH, Heraeus Deutschland Gmbh & Co. KG, ALANOD GmbH & Co. KG
    Inventors: Jörg Erich Sorg, Stefan Ziegler, Michael Austgen, Alexander Peetsch, Eckhard Ditzel, Michael Benedikt
  • Publication number: 20190097106
    Abstract: A connection carrier, an optoelectronic component and a method for producing a connection carrier or an optoelectronic component are disclosed. In an embodiment a connection carrier includes a substrate, an electrically insulating connecting element, an electrically conductive contact element and an insulation element.
    Type: Application
    Filed: February 10, 2017
    Publication date: March 28, 2019
    Inventors: Eckhard Ditzel, Tihomir Klajic, Reiner Windisch, Andreas Biebersdorf
  • Patent number: 10176420
    Abstract: A strip-type substrate includes a foil having a number of substrate units for producing chip card modules. The substrate has an inner face for at least partial direct or indirect contacting of a semiconductor chip and an outer face lying opposite the inner face. The foil includes of steel, in particular high-grade steel, and a first layer of nickel or a nickel alloy on at least some sections of the outer face.
    Type: Grant
    Filed: February 17, 2016
    Date of Patent: January 8, 2019
    Assignee: HERAEUS DEUTSCHLAND GMBH & CO. KG
    Inventors: Eckhard Ditzel, Bernd Gehlert, Frank Krüger
  • Publication number: 20180138379
    Abstract: A method of producing at least one connection carrier includes: A) providing a carrier plate with a planar top face; B) applying at least one electrically insulating insulation strip to the top face and cohesively connecting the carrier plate and the insulation strip; and C) applying at least one electrically conductive conductor strip to an adhesive surface of the insulation strip and cohesively connecting the insulation strip and the conductor strip, wherein the conductor strip and the carrier plate are electrically insulated from one another by the insulation strip.
    Type: Application
    Filed: April 19, 2016
    Publication date: May 17, 2018
    Inventors: Jörg Erich Sorg, Stefan Ziegler, Michael Austgen, Alexander Peetsch, Eckhard Ditzel, Michael Benedikt
  • Patent number: 9941197
    Abstract: A strip-shaped substrate made from a film includes a plurality of units for producing chip carriers. Each unit has a chip island for fixing a semiconductor chip, electrodes for electrical connection of the semiconductor chip, and through-openings for structuring the unit. At least one through-opening forms an anchoring edge for a casting compound for encapsulating the semiconductor chip. A surface section of the film abutting the through-opening is chamfered to form the anchoring edge. The anchoring edge protrudes past the side of the film on which the chip island is arranged.
    Type: Grant
    Filed: June 15, 2015
    Date of Patent: April 10, 2018
    Assignee: HERAEUS DEUTSCHLAND GMBH & CO. KG
    Inventors: Eckhard Ditzel, Siegfried Walter, Michael Benedikt, Udo Becker
  • Publication number: 20180039875
    Abstract: A strip-type substrate includes a foil having a number of substrate units for producing chip card modules. The substrate has an inner face for at least partial direct or indirect contacting of a semiconductor chip and an outer face lying opposite the inner face. The foil includes of steel, in particular high-grade steel, and a first layer of nickel or a nickel alloy on at least some sections of the outer face.
    Type: Application
    Filed: February 17, 2016
    Publication date: February 8, 2018
    Applicant: Heraeus Deutschland GmbH & Co. KG
    Inventors: Eckhard DITZEL, Bernd GEHLERT, Frank KRÜGER
  • Patent number: 9756730
    Abstract: A laminate and method for producing the laminate are provided for contacting at least one electronic component. An insulating layer is laminated between first and second metal layers electrically contacted to each other in at least one contact region. At least one recess in the contact region is generated with at least one embossing and/or bulging in the first metal layer. The distance between the two metal layers is reduced, such that dimensions of the embossing/bulging are sufficient for taking up the electronic component, which is inserted and connected into the embossing/bulging in a conductive manner therein. The electronic component is taken up in the embossing/bulging entirely with respect to its circumference and at least partly with respect to the height (H) of the electronic component. The laminate may be used as a circuit board, sensor, LED lamp, mobile phone component, control, or regulator.
    Type: Grant
    Filed: October 21, 2011
    Date of Patent: September 5, 2017
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventors: Andreas Steffen Klein, Eckhard Ditzel, Frank Krüger, Michael Schumann
  • Publication number: 20170133313
    Abstract: A strip-shaped substrate made from a film includes a plurality of units for producing chip carriers. Each unit has a chip island for fixing a semiconductor chip, electrodes for electrical connection of the semiconductor chip, and through-openings for structuring the unit. At least one through-opening forms an anchoring edge for a casting compound for encapsulating the semiconductor chip. A surface section of the film abutting the through-opening is chamfered to form the anchoring edge. The anchoring edge protrudes past the side of the film on which the chip island is arranged.
    Type: Application
    Filed: June 15, 2015
    Publication date: May 11, 2017
    Applicant: Heraeus Deutschland GmbH & Co. KG
    Inventors: Eckhard DITZEL, Siegfried WALTER, Michael BENEDIKT, Udo BECKER
  • Patent number: 9048393
    Abstract: An optoelectronic component including a connection carrier including an electrically insulating film at a top side of the connection carrier, an optoelectronic semiconductor chip at the top side of the connection carrier, a cutout in the electrically insulating film which encloses the optoelectronic semiconductor chip, and a potting body surrounding the optoelectronic semiconductor chip, wherein a bottom area of the cutout is formed at least regionally by the electrically insulating film, the potting body extends at least regionally as far as an outer edge of the cutout facing the optoelectronic semiconductor chip, and the cutout is at least regionally free of the potting body.
    Type: Grant
    Filed: May 28, 2010
    Date of Patent: June 2, 2015
    Assignees: OSRAM Opto Semiconductor GmbH, Heraeus Materials Technology GmbH & Co. KG
    Inventors: Michael Zitzlsperger, Eckhard Ditzel, Jörg Erich Sorg
  • Publication number: 20130223032
    Abstract: A laminate and method for producing the laminate are provided for contacting at least one electronic component. An insulating layer is laminated between first and second metal layers electrically contacted to each other in at least one contact region. At least one recess in the contact region is generated with at least one embossing and/or bulging in the first metal layer. The distance between the two metal layers is reduced, such that dimensions of the embossing/bulging are sufficient for taking up the electronic component, which is inserted and connected into the embossing/bulging in a conductive manner therein. The electronic component is taken up in the embossing/bulging entirely with respect to its circumference and at least partly with respect to the height (H) of the electronic component. The laminate may be used as a circuit board, sensor, LED lamp, mobile phone component, control, or regulator.
    Type: Application
    Filed: October 21, 2011
    Publication date: August 29, 2013
    Applicants: OSRAM OPTO SEMICONDUCTORS GMBH, HERAEUS MATERIALS TECHNOLOGY GMBH & CO. KG
    Inventors: Andreas Steffen Klein, Eckhard Ditzel, Frank Krüger, Michael Schumann
  • Publication number: 20130215584
    Abstract: The invention relates to methods for producing a laminate for contacting an electronic component, in which an insulating layer is arranged between first and second metal layers. The method includes contacting the metal layers to each other in a contact region, generating a recess in the insulating layer, laminating the metal layers to the insulating layer, generating a notch for accommodating the electronic component in the contact region in the first metal layer, inserting the electronic component in a depression in the laminate formed through a notch and recess. The electronic component is connected in a conductive manner to the second metal layer, such that an entire circumference of the electronic component is accommodated in the recess and/or notch, and at least part of the height of the electronic component is accommodated in the notch and/or recess. The invention also relates to such a laminate for contacting an electronic component.
    Type: Application
    Filed: October 24, 2011
    Publication date: August 22, 2013
    Applicant: HERAEUS MATERIALS TECHNOLOGY GMBH & CO. KG
    Inventors: Andreas Klein, Eckhard Ditzel, Frank Krüger, Wulf Kock, Andreas Hinrich
  • Publication number: 20120139003
    Abstract: An optoelectronic component including a connection carrier including an electrically insulating film at a top side of the connection carrier, an optoelectronic semiconductor chip at the top side of the connection carrier, a cutout in the electrically insulating film which encloses the optoelectronic semiconductor chip, and a potting body surrounding the optoelectronic semiconductor chip, wherein a bottom area of the cutout is formed at least regionally by the electrically insulating film, the potting body extends at least regionally as far as an outer edge of the cutout facing the optoelectronic semiconductor chip, and the cutout is at least regionally free of the potting body.
    Type: Application
    Filed: May 28, 2010
    Publication date: June 7, 2012
    Applicants: HERAEUS MATERIALS TECHNOLOGY GMBH & CO. KG, OSRAM OPTO SEMICONDUCTORS GMBH
    Inventors: Michael Zitzlsperger, Eckhard Ditzel, Jörg Erich Sorg
  • Patent number: 8153232
    Abstract: A method is provided for producing a laminated substrate for mounting semiconductor chips. At least respective metal and plastic structure films having respective different recurrent contours are laminated together in such a way that a material strip is obtained. The lamination is followed by perforations or cuttings, and the method includes at least one of the following steps: A. the films are structured in such a way that superposition thereof makes it possible to obtain the areas which are devoid of overlap through the total width thereof; B. the films are not laminated through the total width of the laminate in partly recurrent areas; and C. recurrent segments of the recurrent contours are bent out of the surface of the laminated strip starting from the laminate.
    Type: Grant
    Filed: March 13, 2008
    Date of Patent: April 10, 2012
    Assignee: W.C. Heraeus GmbH
    Inventors: Eckhard Ditzel, Siegfried Walter, Manfred Gresch
  • Publication number: 20080220202
    Abstract: A method is provided for producing a laminated substrate for mounting semiconductor chips. At least respective metal and plastic structure films having respective different recurrent contours are laminated together in such a way that a material strip is obtained. The lamination is followed by perforations or cuttings, and the method includes at least one of the following steps: A. the films are structured in such a way that superposition thereof makes it possible to obtain the areas which are devoid of overlap through the total width thereof; B. the films are not laminated through the total width of the laminate in partly recurrent areas; and C. recurrent segments of the recurrent contours are bent out of the surface of the laminated strip starting from the laminate.
    Type: Application
    Filed: March 13, 2008
    Publication date: September 11, 2008
    Applicant: W.C. HERAEUS GMBH
    Inventors: Eckhard DITZEL, Siegfried WALTER, Manfred GRESCH
  • Patent number: 5496140
    Abstract: A blind rivet includes a mandrel shaft having a head disposed at one axial end. A hollow rivet shell has a cylindrical shape including an inner cylindrical surface and an outer cylindrical surface. The rivet shell surrounds the mandrel shaft. The outer cylindrical surface has at least one attenuation groove, which includes at least two recesses. Each recess has a bottom surface that substantially forms a secant with respect to the outer cylindrical surface. A method of manufacturing a blind rivet comprises the steps of placing a mandrel shaft having a head within a hollow rivet shell, producing at least one attenuation groove in an outer cylindrical surface of the rivet shell after the placing step so that at least two recesses are formed. Each of the recesses has a bottom surface that substantially forms a secant with respect to the outer cylindrical surface.
    Type: Grant
    Filed: December 8, 1994
    Date of Patent: March 5, 1996
    Assignee: Gesipa Blindniettechnik GmbH
    Inventors: Richard Gossmann, Eckhard Ditzel