Abstract: A functional testing high-speed serial link system includes a testing controller that generates a functional testing program, and a device under test (DUT) that receives the functional testing program. The DUT includes a first logic circuit array that generates first results in response to executing the functional test program. The system also includes a supporting chip that receives the functional testing program. The supporting chip includes a second logic circuit array that generates second results in response to executing the functional test program. A physical data link establishes signal communication between the DUT and the supporting chip. The testing controller diagnoses the physical link based on a comparison between expected diagnostic results associated with the functional testing program, and at least one of the first results and the second results.

Abstract: A functional testing high-speed serial link system includes a testing controller that generates a functional testing program, and a device under test (DUT) that receives the functional testing program. The DUT includes a first logic circuit array that generates first results in response to executing the functional test program. The system also includes a supporting chip that receives the functional testing program. The supporting chip includes a second logic circuit array that generates second results in response to executing the functional test program. A physical data link establishes signal communication between the DUT and the supporting chip. The testing controller diagnoses the physical link based on a comparison between expected diagnostic results associated with the functional testing program, and at least one of the first results and the second results.

Abstract: A method for electrical testing of a 3-D integrated circuit chip stack is described. The 3-D integrated circuit chip stack comprises at least a first integrated circuit chip and a second integrated circuit chip. The first integrated circuit chip and the second integrated circuit chip are not soldered together for performing electrical testing.

Abstract: A test probe aligner for aligning a test probe card with devices under test of a wafer is provided. The test probe aligner includes a backer plate arranged with its bottom side to the test probe card, and a stiffener mounted to the test probe card outside a horizontal dimension of the backer plate. The stiffener and a top side of the backer plate end in a same plane above the test probe card. The alignment further includes a bridge beam locked to a top side of the stiffener. Furthermore, the test probe aligner also includes at least two actuators and at least two corresponding force measurement sensors below a top surface of the bridge beam, arranged such that forces are applicable to the test probe card.

Abstract: A module plate is provided for use with a wafer handler and testing mechanism. The module plate has a diameter equivalent to an integrated circuit wafer and a height equivalent to or less than a height of a module lid associated with each module in a plurality of modules associated with the module plate. The module plate has a plurality of cutouts in the module plate that have a width equivalent to a width of the module lid and at least a length equivalent to a length of the module lid. The height of the module plate is such that, when a test head contacts a module base of each module in a plurality of modules, the module lid contacts a chuck on which the module plate resides during testing of the module thereby providing resistance in order to accurately test the module.

Abstract: A module plate is provided for use with a wafer handler and testing mechanism. The module plate has a diameter equivalent to an integrated circuit wafer and a height equivalent to or less than a height of a module lid associated with each module in a plurality of modules associated with the module plate. The module plate has a plurality of cutouts in the module plate that have a width equivalent to a width of the module lid and at least a length equivalent to a length of the module lid. The height of the module plate is such that, when a test head contacts a module base of each module in a plurality of modules, the module lid contacts a chuck on which the module plate resides during testing of the module thereby providing resistance in order to accurately test the module.

Abstract: A backing apparatus for use in a semiconductor automatic test equipment including: a probe card holder configured to rigidly affix one or more first portions of a flexible probe card to the probe card holder, wherein a respective back side of each of the one or more first portions is adjacent to the probe card holder when the one or more portions are rigidly affixed to the probe card holder; linear actuators; and a rigid backing plate configured to rigidly affix a second portion of the flexible probe card to the rigid backing plate, wherein one side of the rigid backing plate is adjacent to a back side of the second portion when the second portion is rigidly affixed to the rigid backing plate, wherein each linear actuator is configured to provide backing of another side of the rigid backing plate against the probe card holder.

Abstract: A test probe aligner for aligning a test probe card with devices under test of a wafer is provided. The test probe aligner includes a backer plate arranged with its bottom side to the test probe card, and a stiffener mounted to the test probe card outside a horizontal dimension of the backer plate. The stiffener and a top side of the backer plate end in a same plane above the test probe card. The alignment further includes a bridge beam locked to a top side of the stiffener. Furthermore, the test probe aligner also includes at least two actuators and at least two corresponding force measurement sensors below a top surface of the bridge beam, arranged such that forces are applicable to the test probe card.

Abstract: A module plate is provided for use with a wafer handler and testing mechanism. The module plate has a diameter equivalent to an integrated circuit wafer and a height equivalent to or less than a height of a module lid associated with each module in a plurality of modules associated with the module plate. The module plate has a plurality of cutouts in the module plate that have a width equivalent to a width of the module lid and at least a length equivalent to a length of the module lid. The height of the module plate is such that, when a test head contacts a module base of each module in a plurality of modules, the module lid contacts a chuck on which the module plate resides during testing of the module thereby providing resistance in order to accurately test the module.

Abstract: A module plate is provided for use with a wafer handler and testing mechanism. The module plate has a diameter equivalent to an integrated circuit wafer and a height equivalent to or less than a height of a module lid associated with each module in a plurality of modules associated with the module plate. The module plate has a plurality of cutouts in the module plate that have a width equivalent to a width of the module lid and at least a length equivalent to a length of the module lid. The height of the module plate is such that, when a test head contacts a module base of each module in a plurality of modules, the module lid contacts a chuck on which the module plate resides during testing of the module thereby providing resistance in order to accurately test the module.

Abstract: A method for soldering three-dimensional integrated circuits is provided. A three-dimensional integrated circuit is heated to a base temperature, wherein the base temperature is lower than the melting point of a solder, and wherein the three-dimensional integrated circuit includes a plurality of solder bumps. A first on-chip heat source reflows a first portion of the plurality of solder bumps that is within a first local-hot-zone. A second on-chip heat source reflows a second portion of the plurality of solder bumps that is within a second local-hot-zone.

Abstract: A method for soldering three-dimensional integrated circuits is provided. A three-dimensional integrated circuit is heated to a base temperature, wherein the base temperature is lower than the melting point of a solder, and wherein the three-dimensional integrated circuit includes a plurality of solder bumps. A first on-chip heat source reflows a first portion of the plurality of solder bumps that is within a first local-hot-zone. A second on-chip heat source reflows a second portion of the plurality of solder bumps that is within a second local-hot-zone.

Abstract: A method for electrical testing of a 3-D integrated circuit chip stack is described. The 3-D integrated circuit chip stack comprises at least a first integrated circuit chip and a second integrated circuit chip. The first integrated circuit chip and the second integrated circuit chip are not soldered together for performing electrical testing.

Abstract: A method for electrical testing of a 3-D integrated circuit chip stack is described. The 3-D integrated circuit chip stack comprises at least a first integrated circuit chip and a second integrated circuit chip. The first integrated circuit chip and the second integrated circuit chip are not soldered together for performing electrical testing.

Abstract: A backing apparatus for use in a semiconductor automatic test equipment including: a probe card holder configured to rigidly affix one or more first portions of a flexible probe card to the probe card holder, wherein a respective back side of each of the one or more first portions is adjacent to the probe card holder when the one or more portions are rigidly affixed to the probe card holder; linear actuators; and a rigid backing plate configured to rigidly affix a second portion of the flexible probe card to the rigid backing plate, wherein one side of the rigid backing plate is adjacent to a back side of the second portion when the second portion is rigidly affixed to the rigid backing plate, wherein each linear actuator is configured to provide backing of another side of the rigid backing plate against the probe card holder.

Abstract: A method for electrical testing of a 3-D integrated circuit chip stack is described. The 3-D integrated circuit chip stack comprises at least a first integrated circuit chip and a second integrated circuit chip. The first integrated circuit chip and the second integrated circuit chip are not soldered together for performing electrical testing.

Abstract: The present invention discloses a foil keyboard with a security system for detecting and preventing unauthorized mechanical access to the key contacts. The foil keyboard comprising a foil having for each key an elastic key spring area in which an electrical contact is arranged, a printed circuit board (PCB) having electrical contacts that are contacted by the electrical contacts of the keys during the key travel, and a security system which is fully integrated into the foil and the PCB. A closed circuit between keyboard foil and PCB forms a security grid that secures that unauthorized mechanical accesses against key contacts are recognized.

Abstract: The present invention contemplates a secure and auditable assembly process for security keyboards which comprises a first country-independent assembly process at the security keyboard manufacturer (SKM) side resulting in country-independent assembled parts, a second and final country-specific assembly process at the ATM manufacturer side resulting in a final assembly of the country-independent parts with their appropriate country-specific layout parts to a complete security keyboard, and a final authentication process at the ATM manufacturer side for activation of the security functions of the assembled security keyboard by the authorized ATM manufacturer.

Abstract: The present invention discloses a foil keyboard with a security system for detecting and preventing unauthorized mechanical access to the key contacts. The foil keyboard comprising a foil having for each key an elastic key spring area in which an electrical contact is arranged, a printed circuit board (PCB) having electrical contacts that are contacted by the electrical contacts of the keys during the key travel, and a security system which is fully integrated into the foil and the PCB. A closed circuit between keyboard foil and PCB forms a security grid that secures that unauthorized mechanical accesses against key contacts are recognized.

Abstract: A method and apparatus for safe and fast turning of a page in a book is taught which is more flexible with respect to the varying characteristics of the applied books, is independent of the mechanical and electrical tolerances of the system and from system wear and tear. The method comprises the steps of: applying an initial value of a contact force between a page lifter and the page and/or an initial value of a contact time for the contact between the page lifter and the page, and increasing the value of the contact force and/or contact time when no page has been lifted during a page turning procedure; whereby the last applied value of the contact force and/or contact time is applicable as the initial value when a next page is provided to be turned over.