Abstract: Binary information is written to and read from a memory cell field forming a matrix-type field of rows and columns via a plurality of write/read circuits, each having a latch flipflop with at least one data terminal connected on one side to an allocated column-related bit line and on the other side, by way of a gate circuit, to a data line. Access to the relevant bit line is accomplished via a column selection signal which controls the gate circuit. A switching device facilitates the writing process. After the excitation of any row-related word line, the switching device interrupts the current supply of the latch flipflops that are selected for an access starting no earlier than when the relevant latch flipflop assumes a state indicating the information content of the accessed memory cell and, at the latest, during the active interval of the relevant column selection signal.