Patents by Inventor Ed A. Varga

Ed A. Varga has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210130652
    Abstract: According to one embodiment, a process for applying an adhesive material onto a barrier sheet substrate is provided. The process includes providing an adhesive material having viscosity of at least about 10,000 centipoise at 250° F. The adhesive material is applied to a multitude of cavities on a surface of a first tool with a coater unit in close proximity to the surface. The adhesive material is transferred from the surface of the first tool to the substrate supported on a surface of a second tool and pressed against the surface of the first tool.
    Type: Application
    Filed: April 30, 2018
    Publication date: May 6, 2021
    Inventors: Kevin CHOU, Patrick EATON, Khaled EL-TAHLAWY, Peter ELAFROS, William R. MYER, George STAMATOUKOS, Ed VARGAS
  • Patent number: 7411289
    Abstract: A process for fabricating an integrated circuit package includes: selectively etching a leadframe strip to define a die attach pad and at least one row of contact pads; mounting a semiconductor die to one side of the leadframe strip, on the die attach pad; wire bonding the semiconductor die to ones of the contact pads; releasably clamping the leadframe strip in a mold by releasably clamping the contact pads; molding in a molding compound to cover the semiconductor die, the wire bonds and a portion of the contact pads not covered by the clamping; releasing the leadframe strip from the mold; depositing a plurality of external contacts on the one side of the leadframe strip, on the contact pads, such that the external contacts protrude from the molding compound; mounting at least one of an active and a passive component to a second side of said leadframe strip; and singulating to provide the integrated circuit package.
    Type: Grant
    Filed: July 15, 2004
    Date of Patent: August 12, 2008
    Assignee: ASAT Ltd.
    Inventors: Neil McLellan, Geraldine Tsui Yee Lin, Chun Ho Fan, Mohan Kirloskar, Ed A. Varga
  • Patent number: 7091581
    Abstract: A process for fabricating an integrated circuit package includes: selectively etching a leadframe strip to define a die attach pad and at least one row of contact pads; mounting a semiconductor die to one side of the leadframe strip, on the die attach pad; wire bonding the semiconductor die to ones of the contact pads; releasably clamping the leadframe strip in a mold by releasably clamping the contact pads; molding in a molding compound to cover the semiconductor die, the wire bonds and a portion of the contact pads not covered by the clamping; releasing the leadframe strip from the mold; depositing a plurality of external contacts on the one side of the leadframe strip, on the contact pads, such that the external contacts protrude from the molding compound; and singulating to provide the integrated circuit package.
    Type: Grant
    Filed: June 14, 2004
    Date of Patent: August 15, 2006
    Assignee: ASAT Limited
    Inventors: Neil McLellan, Geraldine Tsui Yee Lin, Chun Ho Fan, Mohan Kirloskar, Ed A. Varga