Patents by Inventor Ed Chenoweth

Ed Chenoweth has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5751151
    Abstract: An integrated circuit test apparatus employs a main test circuit load board which has a circular array of relay card mounts located on it. Auxiliary relays, operated in conjunction with the load board, are mounted in groups on individual relay circuit cards, each card including several relays. The relay circuit cards have connectors on first and second edges thereof; and the connectors on the first edges interconnect with the corresponding receptacles on the relay card mounts. A customized configuration board load ring for the particular integrated circuit device under test (DUT) then is placed over the second edges of the relay circuit cards to interconnect with spring-loaded connectors on these edges to effect the configuration for the operation of the particular DUT which is undergoing test at any given time.
    Type: Grant
    Filed: April 12, 1996
    Date of Patent: May 12, 1998
    Assignee: VLSI Technology
    Inventors: Paul S. Levy, Ed Chenoweth