Abstract: The invention relates primarily to wafer-scale integration. Yet in one aspect, circuitry is provided to enable dicing of the wafer to use discrete memory sections thereon as memory chips should the wafer as a whole fail test. In another aspect, error detection and correction circuitry is provided within the street area to detect and correct errors generated within the discrete memory sections where wafer-scale integration manufacturing is successful. In another aspect, clusters of discrete sections of integrated circuitry are provided which include RAM integrated circuitry. One discrete section within the cluster comprises a) control circuitry to control and coordinate operation of discrete sections within the cluster, and b) error detection and correction circuitry to detect and correct errors generated within the discrete sections of RAM integrated circuitry.

Abstract: Disclosed is a method for producing individual semiconductor chips which are singulated from larger wafers, and singulated wafers produced according to the method. Wafers from which the singulated dies are produced include scribe line area through which the wafer is cut by a saw or other method for singulating individual dies. In one aspect of the invention, test pads are provided within the scribe line area for testing of individual dies prior to severing of the wafer. In another aspect of the invention, conventional test circuitry is formed within the scribe line area and utilized in conjunction with text pads for testing operability of individual wafers prior to severing of the wafer into individual chips. Upon test, the scribe lines are severed effectively destroying the sacrificial test pads and circuitry.