Patents by Inventor Ed Paulsen

Ed Paulsen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Test IP-based A.T.E. instrument architecture
    Patent number: 9910086
    Abstract: A test system based on multiple instances of reconfigurable instrument IP specifically matched to the device under test may be used in integrating automated testing of semiconductor devices between pre-silicon simulation, post-silicon validation, and production test phases, in one embodiment of software and hardware across all three phases, for different devices. The reconfigurable test system comprises: a tester instrument, instances of instrument IP instantiated in the tester instruments, a computer system, and a test program. The tester instrument connects to a device under test (DUT), and includes FPGAs reconfigurable for the three testing phases. The computer system has a user interface, and a controller connected to the reconfigurable tester instrument via a data bus.
    Type: Grant
    Filed: January 28, 2016
    Date of Patent: March 6, 2018
    Inventors: Allen Czamara, Ed Paulsen, Lev Alperovich
  • Test IP-Based A.T.E. Instrument Architecture
    Publication number: 20160238657
    Abstract: A test system based on multiple instances of reconfigurable instrument IP specifically matched to the device under test may be used in integrating automated testing of semiconductor devices between pre-silicon simulation, post-silicon validation, and production test phases, in one embodiment of software and hardware across all three phases, for different devices. The reconfigurable test system comprises: a tester instrument, instances of instrument IP instantiated in the tester instruments, a computer system, and a test program. The tester instrument connects to a device under test (DUT), and includes FPGAs reconfigurable for the three testing phases. The computer system has a user interface, and a controller connected to the reconfigurable tester instrument via a data bus.
    Type: Application
    Filed: January 28, 2016
    Publication date: August 18, 2016
    Inventors: Allen Czamara, Ed Paulsen, Lev Alperovich
  • Test IP-Based A.T.E. Instrument Architecture
    Publication number: 20130227367
    Abstract: A test system based on multiple instances of reconfigurable instrument IP specifically matched to the device under test may be used in integrating automated testing of semiconductor devices between pre-silicon simulation, post-silicon validation, and production test phases, in one embodiment of software and hardware across all three phases, for different devices. The reconfigurable test system comprises: a tester instrument, instances of instrument IP instantiated in the tester instruments, a computer system, and a test program. The tester instrument connects to a device under test (DUT), and includes FPGAs reconfigurable for the three testing phases. The computer system has a user interface, and a controller connected to the reconfigurable tester instrument via a data bus.
    Type: Application
    Filed: January 16, 2013
    Publication date: August 29, 2013
    Inventors: Allen J. Czamara, Ed Paulsen, Lev Alperovich