Abstract: A method for detecting an endpoint of a seasoning process in a process chamber includes obtaining seasoning progress data indicating a progress of the seasoning process for each substrate of a first plurality of substrates, and collecting historical parameter values from a plurality of sensors disposed in the process chamber. The historical parameter values for each substrate of the first plurality of substrates are normalized with respect to a plurality of parameter values for a particular substrate in the first plurality of substrates. An MVA model is generated by applying a set of coefficients to the normalized parameter values for each substrate of the first plurality of substrates, and the set of coefficients are regressed based on the seasoning progress data. An end point of the seasoning process is determined using the MVA model with a plurality of substantially real-time parameter values measured when performing a seasoning process over each substrate of a second plurality of substrates.

Abstract: A method for detecting an endpoint of a seasoning process in a process chamber includes obtaining seasoning progress data indicating a progress of the seasoning process for each substrate of a first plurality of substrates, and collecting historical parameter values from a plurality of sensors disposed in the process chamber. The historical parameter values for each substrate of the first plurality of substrates are normalized with respect to a plurality of parameter values for a particular substrate in the first plurality of substrates. An MVA model is generated by applying a set of coefficients to the normalized parameter values for each substrate of the first plurality of substrates, and the set of coefficients are regressed based on the seasoning progress data. An end point of the seasoning process is determined using the MVA model with a plurality of substantially real-time parameter values measured when performing a seasoning process over each substrate of a second plurality of substrates.

Abstract: In one embodiment, an apparatus includes a first gas distribution assembly that includes a first gas passage for introducing a first process gas into a second gas passage that introduces the first process gas into a processing chamber and a second gas distribution assembly that includes a third gas passage for introducing a second process gas into a fourth gas passage that introduces the second process gas into the processing chamber. The first and second gas distribution assemblies are each adapted to be coupled to at least one chamber wall of the processing chamber. The first gas passage is shaped as a first ring positioned within the processing chamber above the second gas passage that is shaped as a second ring positioned within the processing chamber. The gas distribution assemblies may be designed to have complementary characteristic radial film growth rate profiles.

Abstract: Described herein are exemplary apparatuses having multiple gas distribution assemblies in accordance with one embodiment. In one embodiment, the apparatus includes two or more gas distribution assemblies. Each gas distribution assembly has orifices through which at least one process gas is introduced into a processing chamber. The two or more gas distribution assemblies may be designed to have complementary characteristic radial film growth rate profiles.

Abstract: A selective self-aligned dual patterning method. The method includes performing a single lithography operation to form a patterned mask having a narrow feature in a region of a substrate that is to a have pitch-reduced feature and a wide feature in a region of the substrate that is to have a non-pitch-reduced feature. Using the patterned mask, a template mask is formed with a first etch and the patterned mask is then removed from the narrow feature while being retained over the wide feature. The template mask is then thinned with a second etch to introduce a thickness delta in the template mask between the narrow and wide features. A spacer mask is then formed and the thinned narrow template mask is removed to leave a pitch double spacer mask while the thick wide template mask feature is retained to leave a non-pitch reduced mask.

Abstract: A selective self-aligned dual patterning method. The method includes performing a single lithography operation to form a patterned mask having a narrow feature in a region of a substrate that is to a have pitch-reduced feature and a wide feature in a region of the substrate that is to have a non-pitch-reduced feature. Using the patterned mask, a template mask is formed with a first etch and the patterned mask is then removed from the narrow feature while being retained over the wide feature. The template mask is then thinned with a second etch to introduce a thickness delta in the template mask between the narrow and wide features. A spacer mask is then formed and the thinned narrow template mask is removed to leave a pitch double spacer mask while the thick wide template mask feature is retained to leave a non-pitch reduced mask.

Abstract: In one embodiment, a method includes providing a plasma etch reactor including a vacuum chamber and an electrode disposed inside of the chamber, and providing a stack to be etched over the electrode, the stack including a patterned photoresist over a dielectric layer. The method further includes providing a chamber pressure between about 75 mT and about 150 mT, flowing gases including CF4 and CHF3 at a ratio between about 2.5:1 and about 5.0:1 into the chamber, applying RF power to the electrode between about 300 W and about 500 W to form a plasma from the gases, and etching the dielectric layer with the plasma through the patterned photoresist.

Abstract: A method is described for decreasing the critical dimensions of integrated circuit features in which a first masking layer (101) is deposited, patterned and opened in the manner of typical feature etching, and a second masking layer (201) is deposited thereon prior to etching the underlying insulator. The second masking layer is advantageously coated in a substantially conformal manner. Opening the second masking layer while leaving material of the second layer on the sidewalls of the first masking layer as spacers leads to reduction of the feature critical dimension in the underlying insulator. Ashable masking materials, including amorphous carbon and organic materials are removable without CMP, thereby reducing costs. Favorable results are also obtained utilizing more than one masking layer (101, 301) underlying the topmost masking layer (302) from which the spacers are formed. Embodiments are also described in which slope etching replaces the addition of a separate spacer layer.

Abstract: A method is described for decreasing the critical dimensions of integrated circuit features in which a first masking layer (101) is deposited, patterned and opened in the manner of typical feature etching, and a second masking layer (201) is deposited thereon prior to etching the underlying insulator. The second masking layer is advantageously coated in a substantially conformal manner. Opening the second masking layer while leaving material of the second layer on the sidewalls of the first masking layer as spacers leads to reduction of the feature critical dimension in the underlying insulator. Ashable masking materials, including amorphous carbon and organic materials are removable without CMP, thereby reducing costs. Favorable results are also obtained utilizing more than one masking layer (101, 301) underlying the topmost masking layer (302) from which the spacers are formed. Embodiments are also described in which slope etching replaces the addition of a separate spacer layer.