Patents by Inventor Edberg Fang

Edberg Fang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20020137329
    Abstract: A method is directed to forming a barrier layer, particularly suitable for use in a copper fabrication process. A substrate is provided. A conductive structure layer may have already been formed on the substrate. An inter-metal dielectric layer is formed over the substrate. The inter-metal dielectric layer is then patterned to form an opening that exposes the substrate. An oxygen getter layer is formed over the inter-metal dielectric layer and the opening. A barrier layer is formed on the oxygen getterlayer. A copper layer is deposited over the barrier layer. An oxidation of the oxygen getter layer is occurred in the subsequent high temperature steps. An oxide layer, serving as another barrier layer, is formed thereon. The oxygen getter layer includes any metal which can easily react with oxygen, such as titanium or tantalum.
    Type: Application
    Filed: May 20, 2002
    Publication date: September 26, 2002
    Inventors: Edberg Fang, Wen-Yi Hsieh, Tri-Rung Yew
  • Patent number: 6316323
    Abstract: The proposed invention is used to prevent the bridging issue of salicide process and also to provide a self-aligned contacted process in conventional self-aligned silicide process.
    Type: Grant
    Filed: March 21, 2000
    Date of Patent: November 13, 2001
    Assignee: United Microelectronics Corp.
    Inventors: Edberg Fang, Wen-Yi Hsieh, Teng-Chun Tsai
  • Patent number: 6255177
    Abstract: A fabrication method for a salicide gate is described, wherein the method comprising forming a gate structure on a substrate. The gate structure comprises a polysilicon gate and a selective-deposition dummy layer formed on the polysilicon gate. Source/drain regions are then formed on both sides of the gate structure in the substrate. After this, a dielectric layer is selectively deposited on the substrate, wherein the dielectric layer on the source/drain regions is thicker than the dielectric layer on the anti-reflection layer. A portion of the dielectric layer is removed until the anti-reflection layer is exposed. The anti-reflection layer is subsequently removed, followed by forming a salicide layer on the polysilicon gate to complete the manufacturing of a salicide gate.
    Type: Grant
    Filed: May 9, 2000
    Date of Patent: July 3, 2001
    Assignee: United Microelectronics Corp.
    Inventors: Edberg Fang, Wen-Yi Hsieh
  • Patent number: 6251711
    Abstract: The proposed invention is a salicide process that is used to avoid bridge phenomena.
    Type: Grant
    Filed: March 17, 2000
    Date of Patent: June 26, 2001
    Assignee: United Microelectronics Corp.
    Inventors: Edberg Fang, Wen-Yi Hsieh, Teng-Chun Tsai
  • Patent number: 6251778
    Abstract: A method for using CMP processes in the salicide process for preventing bridging.
    Type: Grant
    Filed: December 1, 1999
    Date of Patent: June 26, 2001
    Assignee: United Microelectronics Corporation
    Inventors: Edberg Fang, T. C. Tsai, L. M. Liu