Abstract: A reflective diffraction grating and a fabrication method are provided. The reflective diffraction grating includes a substrate, a UV-absorbing layer, a grating layer having a binary surface-relief pattern formed therein, and a conforming reflective layer. Advantageously, the UV-absorbing layer absorbs light at a UV recording wavelength to minimize reflection thereof by the substrate during holographic patterning at the UV recording wavelength.

Abstract: A reflective diffraction grating and a fabrication method are provided. The reflective diffraction grating includes a substrate, a UV-absorbing layer, a grating layer having a binary surface-relief pattern formed therein, and a conforming reflective layer. Advantageously, the UV-absorbing layer absorbs light at a UV recording wavelength to minimize reflection thereof by the substrate during holographic patterning at the UV recording wavelength.

Abstract: A reflective diffraction grating and a fabrication method are provided. The reflective diffraction grating includes a substrate, a UV-absorbing layer, a grating layer having a binary surface-relief pattern formed therein, and a conforming reflective layer. Advantageously, the UV-absorbing layer absorbs light at a UV recording wavelength to minimize reflection thereof by the substrate during holographic patterning at the UV recording wavelength.

Abstract: A reflective diffraction grating and a fabrication method are provided. The reflective diffraction grating includes a substrate, a UV-absorbing layer, a grating layer having a binary surface-relief pattern formed therein, and a conforming reflective layer. Advantageously, the UV-absorbing layer absorbs light at a UV recording wavelength to minimize reflection thereof by the substrate during holographic patterning at the UV recording wavelength.

Abstract: A method is disclosed for removing a polysilicon layer from a semiconductor wafer, in which a downstream plasma source is used first to planarize the wafer, removing contours in the polysilicon layer caused by deposition over lithographic features, such as via holes. The planarizing process is followed by exposure to a plasma made by a direct, radio frequency plasma source, which may be in combination with the downstream plasma source, to perform the bulk etching of the polysilicon. The invention can produce planar surface topography after the top layer of the film is removed, in which the residual recess height of the polysilicon plug filling a via hole is less than about about 10 nm.

Abstract: The present invention pertains to methods for cleaning semiconductor wafers, more specifically, for removing polymeric and other residues from a wafer using dry plasmas generated with microwave (MW), electromagnetic field (inductively-coupled plasma (ICP)), and radio frequency (RF) energy. First, a wafer is treated by applying a microwave-generated plasma or an inductively-coupled plasma. Second, a radio frequency generated plasma is applied. Each of the microwave-generated plasma and the inductively-coupled plasma is produced from a gas mixture, which includes an oxygen source gas, a fluorine source gas, and a hydrogen source gas. Using such plasmas provides more controllable etch rates than conventional plasmas via control of fluorine concentration in the plasma. Application of a radio frequency generated (preferably oxygen-based) plasma is used for additional photoresist and polymer removal.

Abstract: A structure or a process of the via chain is employed to test the misalignment. The structure of the via chain includes a first via chain in the first direction and a second via chain in the second direction. Using the structure having the via chains in two different directions, the misalignment can be easily detected.

Abstract: A switch mode power supply (200, FIG. 2; 600, FIG. 6) includes a transformer (208), a transistor (212) that drives the primary winding of the transformer, and a controller (210, 610). The controller senses whether or not the transformer is reset and applies a switching control signal to a control terminal (220) of the transistor, accordingly. The signal is produced at a switching frequency, and the signal has a duty cycle that is limited based on whether or not the transformer is reset.

Abstract: A method for forming a contact plug that lands on a metal line of an interconnect structure formed on a semiconductor substrate. First, a first insulating layer is formed atop the substrate and between gaps in the interconnect structure. Next, an etching stop layer is formed on the first insulating layer. A second insulating layer is formed atop the etching stop layer. The second insulating layer is patterned and etched, stopping at the etching stop layer, to form a contact opening. The portion of the etching stop layer left exposed by the contact opening is removed. Finally, a barrier metal layer is formed along the walls of the contact opening and a conducting layer is deposited into the contact opening.

Abstract: A method for improving profile control during an etch of a nitride layer disposed above a silicon substrate is disclosed. The nitride layer 106 is disposed below a photoresist mask 108A. The method includes positioning the substrate, including the nitride layer and the photoresist mask, in a plasma processing chamber. There is also included flowing a chlorine-containing etchant source gas into the plasma processing chamber. Further, there is included igniting a plasma out of the chlorine-containing etchant source gas to form a chlorine-based plasma within the plasma processing chamber. Additionally, there is included treating, using a chlorine-based plasma, the photoresist mask in the plasma processing chamber. The treatment of the photoresist is configured to etch at least a portion of the photoresist mask and to deposit passivation polymer on vertical sidewalls of the photoresist mask without etching through the nitride layer.