Patents by Inventor Eddie Williamson

Eddie Williamson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7327148
    Abstract: Capacitive leadframe testing techniques are improved through knowledge of characteristics of semiconductor junctions specific to nodes of device under test (DUT) that are connected to nodes under test of the DUT.
    Type: Grant
    Filed: June 29, 2005
    Date of Patent: February 5, 2008
    Assignee: Agilent Technologies, Inc.
    Inventors: Myron J. Schneider, Eddie Williamson
  • Patent number: 7242198
    Abstract: Capacitive leadframe testing techniques are improved through knowledge of characteristics of semiconductor junctions specific to nodes of device under test (DUT) that are connected to nodes under test of the DUT.
    Type: Grant
    Filed: June 29, 2006
    Date of Patent: July 10, 2007
    Assignee: Agilent Technologies, Inc.
    Inventors: Myron J. Schneider, Eddie Williamson
  • Publication number: 20070001688
    Abstract: Capacitive leadframe testing techniques are improved through knowledge of characteristics of semiconductor junctions specific to nodes of device under test (DUT) that are connected to nodes under test of the DUT.
    Type: Application
    Filed: June 29, 2006
    Publication date: January 4, 2007
    Inventors: Myron Schnelder, Eddie Williamson
  • Publication number: 20070001687
    Abstract: Capacitive leadframe testing techniques are improved through knowledge of characteristics of semiconductor junctions specific to nodes of device under test (DUT) that are connected to nodes under test of the DUT.
    Type: Application
    Filed: June 29, 2005
    Publication date: January 4, 2007
    Inventors: Myron Schneider, Eddie Williamson
  • Patent number: 7075307
    Abstract: The present invention is a method an apparatus for diagnosing short defects on inaccessible or non-contacted nodes of an integrated circuit device using capacitive coupling techniques. In accordance with the invention, an alternating current (AC) signal generator is connected to apply an alternating current (AC) signal to an accessible node of an IC device under test. Preferably, all remaining accessible nodes of the IC device under test are grounded. A sensor plate of a capacitive sensing probe is placed in signal coupling proximity to the inaccessible node of interest on the integrated circuit device. If a signal is present on the inaccessible node of interest, it is capacitively coupled to the sensor plate of the probe. A measurement device obtains a measurement representative of an amount of current flow capacitively coupled to the sensor plate by the capacitive sensing probe.
    Type: Grant
    Filed: April 22, 2005
    Date of Patent: July 11, 2006
    Assignee: Agilent Technologies, Inc.
    Inventor: Eddie Williamson
  • Patent number: 7057395
    Abstract: A method and apparatus for diagnosing open defects on non-contacted nodes of an electrical device is presented. Actual and expected signal measurements are collected for various contacted nodes of the electrical device. Nodes whose actual measurements are out of range of their respective expected measurements are deemed abnormal nodes. Non-contacted nodes may then be assessed as having, or as likely to have, open defects based on knowledge of the degree of coupling of the non-contacted node to the abnormal contacted nodes. In the preferred embodiment, abnormal nodes are identified using a linear regression analysis, and the non-contacted nodes indicted as having open defects are identified using a weighting scheme.
    Type: Grant
    Filed: March 4, 2005
    Date of Patent: June 6, 2006
    Assignee: Agilent Technologies, Inc.
    Inventor: Eddie Williamson