Patents by Inventor Eddy De Backer
Eddy De Backer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9842899Abstract: A semiconductor wafer can include a substrate, a poly template layer, and a semiconductor layer. The substrate has a central region and an edge region, the poly template layer is disposed along a peripheral edge of the substrate, and a semiconductor layer over the central region, wherein the semiconductor layer is monocrystalline. In an embodiment, the poly template layer and the monocrystalline layer are laterally spaced apart from each other by an intermediate region. In another embodiment, the semiconductor layer can include aluminum. A process of forming the substrate can include forming a patterned poly template layer within the edge region and forming a semiconductor layer over the primary surface. Another process of forming the substrate can include forming a semiconductor layer over the primary surface and removing a portion of the semiconductor layer so that the semiconductor layer is spaced apart from an edge of the substrate.Type: GrantFiled: December 11, 2015Date of Patent: December 12, 2017Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Hocine Bouzid Ziad, Peter Moens, Eddy De Backer
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Publication number: 20160099319Abstract: A semiconductor wafer can include a substrate, a poly template layer, and a semiconductor layer. The substrate has a central region and an edge region, the poly template layer is disposed along a peripheral edge of the substrate, and a semiconductor layer over the central region, wherein the semiconductor layer is monocrystalline. In an embodiment, the poly template layer and the monocrystalline layer are laterally spaced apart from each other by an intermediate region. In another embodiment, the semiconductor layer can include aluminum. A process of forming the substrate can include forming a patterned poly template layer within the edge region and forming a semiconductor layer over the primary surface. Another process of forming the substrate can include forming a semiconductor layer over the primary surface and removing a portion of the semiconductor layer so that the semiconductor layer is spaced apart from an edge of the substrate.Type: ApplicationFiled: December 11, 2015Publication date: April 7, 2016Applicant: Semiconductor Components Industries, LLCInventors: Hocine Bouzid ZIAD, Peter MOENS, Eddy DE BACKER
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Patent number: 9245736Abstract: A semiconductor wafer can include a substrate, a poly template layer, and a semiconductor layer. The substrate has a central region and an edge region, the poly template layer is disposed along a peripheral edge of the substrate, and a semiconductor layer over the central region, wherein the semiconductor layer is monocrystalline. In an embodiment, the poly template layer and the monocrystalline layer are laterally spaced apart from each other by an intermediate region. In another embodiment, the semiconductor layer can include aluminum. A process of forming the substrate can include forming a patterned poly template layer within the edge region and forming a semiconductor layer over the primary surface. Another process of forming the substrate can include forming a semiconductor layer over the primary surface and removing a portion of the semiconductor layer so that the semiconductor layer is spaced apart from an edge of the substrate.Type: GrantFiled: March 10, 2014Date of Patent: January 26, 2016Assignee: Semiconductor Components Industries, LLCInventors: Hocine Bouzid Ziad, Peter Moens, Eddy De Backer
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Publication number: 20140264368Abstract: A semiconductor wafer can include a substrate, a poly template layer, and a semiconductor layer. The substrate has a central region and an edge region, the poly template layer is disposed along a peripheral edge of the substrate, and a semiconductor layer over the central region, wherein the semiconductor layer is monocrystalline. In an embodiment, the poly template layer and the monocrystalline layer are laterally spaced apart from each other by an intermediate region. In another embodiment, the semiconductor layer can include aluminum. A process of forming the substrate can include forming a patterned poly template layer within the edge region and forming a semiconductor layer over the primary surface. Another process of forming the substrate can include forming a semiconductor layer over the primary surface and removing a portion of the semiconductor layer so that the semiconductor layer is spaced apart from an edge of the substrate.Type: ApplicationFiled: March 10, 2014Publication date: September 18, 2014Inventors: Hocine ZIAD, Peter MOENS, Eddy DE BACKER
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Patent number: 8648410Abstract: An electronic device can include a gate electrode and a gate tap that makes an unlanded contact to the gate electrode. The electronic device can further include a source region and a drain region that may include a drift region. In an embodiment, the gate electrode has a height that is greater than its width. In another embodiment, the electronic device can include gate taps that spaced apart from each other, wherein at least some of the gate taps contact the gate electrode over the channel region. In a further embodiment, at a location where the gate tap contacts the gate electrode, the gate tap is wider than the gate electrode. A variety of processes can be used to form the electronic device.Type: GrantFiled: August 6, 2013Date of Patent: February 11, 2014Assignee: Semiconductor Components Industries, LLCInventors: Peter Coppens, Eddy De Backer, Freddy De Pestel, Gordon M. Grivna
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Publication number: 20130320428Abstract: An electronic device can include a gate electrode and a gate tap that makes an unlanded contact to the gate electrode. The electronic device can further include a source region and a drain region that may include a drift region. In an embodiment, the gate electrode has a height that is greater than its width. In another embodiment, the electronic device can include gate taps that spaced apart from each other, wherein at least some of the gate taps contact the gate electrode over the channel region. In a further embodiment, at a location where the gate tap contacts the gate electrode, the gate tap is wider than the gate electrode. A variety of processes can be used to form the electronic device.Type: ApplicationFiled: August 6, 2013Publication date: December 5, 2013Inventors: Peter COPPENS, Eddy De BACKER, Freddy De PESTEL, Gordon M. GRIVNA
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Patent number: 8530304Abstract: An electronic device can include a gate electrode and a gate tap that makes an unlanded contact to the gate electrode. The electronic device can further include a source region and a drain region that may include a drift region. In an embodiment, the gate electrode has a height that is greater than its width. In another embodiment, the electronic device can include gate taps that spaced apart from each other, wherein at least some of the gate taps contact the gate electrode over the channel region. In a further embodiment, at a location where the gate tap contacts the gate electrode, the gate tap is wider than the gate electrode. A variety of processes can be used to form the electronic device.Type: GrantFiled: June 14, 2011Date of Patent: September 10, 2013Assignee: Semiconductor Components Industries, LLCInventors: Peter Coppens, Eddy De Backer, Freddy De Pestel, Gordon M. Grivna
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Publication number: 20120319188Abstract: An electronic device can include a gate electrode and a gate tap that makes an unlanded contact to the gate electrode. The electronic device can further include a source region and a drain region that may include a drift region. In an embodiment, the gate electrode has a height that is greater than its width. In another embodiment, the electronic device can include gate taps that spaced apart from each other, wherein at least some of the gate taps contact the gate electrode over the channel region. In a further embodiment, at a location where the gate tap contacts the gate electrode, the gate tap is wider than the gate electrode. A variety of processes can be used to form the electronic device.Type: ApplicationFiled: June 14, 2011Publication date: December 20, 2012Inventors: Peter Coppens, Eddy De Backer, Freddy De Pestel, Gordon M. Grivna
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Patent number: 6835644Abstract: A method for making interconnect structures, particularly in a semiconductor integrated circuit, is described. The method comprises the steps of: forming a conductive layer; forming of an insulating layer above said conductive layer; creating a plurality of holes in said insulating layer and filling the holes with tungsten thereby forming tungsten plugs, such that said tungsten plugs are in electrical contact with the conductive layer. A patterned metallisation layer that overlies said insulating layer (is formed by means of following steps: forming a continuous metallisation layer, forming an organic mask, etching in plasma said continuous metallisation layer, removing the organic mask in a dry way, and immersing the obtained wafer including the layers (3, 4, 5) and the tungsten plugs in a cleaning solution to remove the post-etching residues. Before immersing into said cleaning solution, the wafer is submitted to a plasma treatment containing F, H or a mixture of F and H.Type: GrantFiled: December 16, 2002Date of Patent: December 28, 2004Assignee: AMI Semiconductor BelgiumInventors: Pierre Stefaan Bruneel, Eddy De Backer, Malik Mastgutovich Fatkhoutdinov
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Publication number: 20040018705Abstract: A method for processing a low ohmic contact structure to a buried conductive layer in or below a device layer forming part of a semiconductor component is presented, whereby first a highly doped region within said device layer reaching said buried conductive layer is realised, this being followed by a step of etching a trench through said highly doped region to a final depth which extends at least to the semiconductor substrate underneath said buried conductive layer. In a variant method this trench is first pre-etched until a predetermined depth, before the highly doped region is provided. A semiconductor structure which is realised by these methods is described as well.Type: ApplicationFiled: March 31, 2003Publication date: January 29, 2004Inventors: Paul Frans Marie Colson, Sylvie Boonen, Eddy De Backer, Freddy Marcel Yvan De Pestel, Peter Dominique Willem Moens, Marnix Roger Anna Tack, Davy Fabien Michel Villanueva
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Publication number: 20040018704Abstract: A method for processing a low ohmic contact structure to a buried conductive layer in or below a device layer forming part of a semiconductor component is presented, whereby first a highly doped region within said device layer reaching said buried conductive layer is realised, this being followed by a step of etching a trench through said highly doped region to a final depth which extends at least to the semiconductor substrate underneath said buried conductive layer. In a variant method this trench is first pre-etched until a predetermined depth, before the highly doped region is provided.Type: ApplicationFiled: July 17, 2003Publication date: January 29, 2004Inventors: Paul Frans Marie Colson, Sylvie Boonen, Eddy De Backer, Freddy Marcel Yvan De Pestel, Peter Dominique Willem Moens, Marnix Roger Anna Tack, Davy Fabien Michel Villanueva
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Publication number: 20030148602Abstract: A method for making interconnect structures, particularly in a semiconductor integrated circuit, comprises the steps of:Type: ApplicationFiled: December 16, 2002Publication date: August 7, 2003Inventors: Pierre Stefaan Bruneel, Eddy De Backer, Malik Mastgutovich Fatkhoutdinov