Patents by Inventor Eddy Wayne CHOW

Eddy Wayne CHOW has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12449444
    Abstract: Presented embodiments facilitate efficient and effective flexible implementation of different types of testing procedures in a test system. In one embodiment, a test system configuration adapter includes a tester side socket, a break out pin, and a device under test side slot. The tester side socket is configured to couple with a test equipment socket. The break out pin is configured to couple with the supplemental equipment. The device under test side slot is configured to couple with the tester side socket, the break out pin, and a device under test, wherein the tester side socket. The test system configuration adapter is configured to enable communication between test equipment coupled to the test equipment socket and supplemental equipment coupled to the breakout pin while the device under test remains coupled to the device under test side slot. In one exemplary implementation, the breakout pin and tester side socket are selectively coupled to the device under test side slot.
    Type: Grant
    Filed: December 4, 2023
    Date of Patent: October 21, 2025
    Assignee: Advantest Corporation
    Inventor: Eddy Wayne Chow
  • Patent number: 12079098
    Abstract: An automated test equipment (ATE) system comprises a system controller communicatively coupled to a tester processor, where the system controller is operable to transmit instructions to the tester processor, and where the tester processor is operable to generate commands and data from the instructions for coordinating testing of a plurality of devices under test (DUTs). The apparatus also comprises an FPGA programmed to support a first protocol communicatively coupled to the tester processor comprising at least one hardware accelerator circuit operable to internally generate commands and data transparently from the tester processor for testing a DUT of the plurality of DUTs. Further, the apparatus comprises a bus adapter comprising a protocol converter module operable to convert signals associated with the first protocol received from the FPGA to signals associated with a second protocol prior to transmitting the signals to the DUT, wherein the DUT communicates using the second protocol.
    Type: Grant
    Filed: December 28, 2020
    Date of Patent: September 3, 2024
    Assignee: Advantest Corporation
    Inventors: Mei-Mei Su, Eddy Wayne Chow, Edmundo De La Puente
  • Publication number: 20240103037
    Abstract: Presented embodiments facilitate efficient and effective flexible implementation of different types of testing procedures in a test system. In one embodiment, a test system configuration adapter includes a tester side socket, a break out pin, and a device under test side slot. The tester side socket is configured to couple with a test equipment socket. The break out pin is configured to couple with the supplemental equipment. The device under test side slot is configured to couple with the tester side socket, the break out pin, and a device under test, wherein the tester side socket. The test system configuration adapter is configured to enable communication between test equipment coupled to the test equipment socket and supplemental equipment coupled to the breakout pin while the device under test remains coupled to the device under test side slot. In one exemplary implementation, the breakout pin and tester side socket are selectively coupled to the device under test side slot.
    Type: Application
    Filed: December 4, 2023
    Publication date: March 28, 2024
    Inventor: Eddy Wayne CHOW
  • Patent number: 11867720
    Abstract: Presented embodiments facilitate efficient and effective flexible implementation of different types of testing procedures in a test system. In one embodiment, a test system configuration adapter includes a tester side socket, a break out pin, and a device under test (DUT) side slot. The tester side socket is configured to couple with a test equipment socket. The break out pin is configured to couple with the supplemental equipment. The DUT side slot is configured to couple with the tester side socket, the break out pin, and a DUT. The test system configuration adapter is configured to enable communication between test equipment coupled to the test equipment socket and supplemental equipment coupled to the breakout pin while the DUT remains coupled to the DUT side slot. The breakout pin and tester side socket can be selectively coupled to the DUT side slot.
    Type: Grant
    Filed: November 16, 2020
    Date of Patent: January 9, 2024
    Assignee: Advantest Corporation
    Inventor: Eddy Wayne Chow
  • Publication number: 20220155342
    Abstract: Presented embodiments facilitate efficient and effective flexible implementation of different types of testing procedures in a test system. In one embodiment, a test system configuration adapter includes a tester side socket, a break out pin, and a device under test side slot. The tester side socket is configured to couple with a test equipment socket. The break out pin is configured to couple with the supplemental equipment. The device under test side slot is configured to couple with the tester side socket, the break out pin, and a device under test, wherein the tester side socket. The test system configuration adapter is configured to enable communication between test equipment coupled to the test equipment socket and supplemental equipment coupled to the breakout pin while the device under test remains coupled to the device under test side slot. In one exemplary implementation, the breakout pin and tester side socket are selectively coupled to the device under test side slot.
    Type: Application
    Filed: November 16, 2020
    Publication date: May 19, 2022
    Inventor: Eddy Wayne CHOW
  • Patent number: 11108640
    Abstract: A method for controlling devices in a de-centralized storage environment comprises partitioning a plurality of devices in a network into a plurality of super-cells, wherein each super-cell comprises a subset of the plurality of devices. For each super-cell, a system controller is configured to nominate a device in the super-cell as a nucleus device, wherein the nucleus device in the super-cell controls member devices in the super-cell. The system controller is further configured to transmit commands associated with a specific task to the nucleus device and receive information from the nucleus device regarding performance of the specific task, wherein the information comprises information aggregated from the member devices of the super-cell associated with a performance of a respective portion of the specific task.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: August 31, 2021
    Assignee: Advantest Corporation
    Inventor: Eddy Wayne Chow
  • Publication number: 20200204447
    Abstract: A method for controlling devices in a de-centralized storage environment comprises partitioning a plurality of devices in a network into a plurality of super-cells, wherein each super-cell comprises a subset of the plurality of devices. For each super-cell, a system controller is configured to nominate a device in the super-cell as a nucleus device, wherein the nucleus device in the super-cell controls member devices in the super-cell. The system controller is further configured to transmit commands associated with a specific task to the nucleus device and receive information from the nucleus device regarding performance of the specific task, wherein the information comprises information aggregated from the member devices of the super-cell associated with a performance of a respective portion of the specific task.
    Type: Application
    Filed: December 20, 2018
    Publication date: June 25, 2020
    Inventor: Eddy Wayne CHOW