Abstract: A method and apparatus for using a 2:1 MUX to control read access, data bypass, and page size bypass in a memory array. The mechanism of the present invention reduces the 3:1 MUX normally required to manage these three functions to a 2:1 MUX.

Abstract: A method and apparatus for using a 2:1 MUX to control read access, data bypass, and page size bypass in a memory array. The mechanism of the present invention reduces the 3:1 MUX normally required to manage these three functions to a 2:1 MUX.

Abstract: An apparatus and method is provided that combines both self test and functional features in a single latch circuit, which may be used with an SRAM array and is usefully embodied as an L1-L2 latch. During partial writes from an SRAM array, data bits of unknown state are inhibited from entering the latch circuit, while data for testing is allowed to enter. In one useful embodiment of the invention the latch circuit is used with a mode control that provides mode select signals to operate the latch circuit in one of a plurality of modes, including at least full write and partial write modes. The latch circuit further includes a data hold circuit for selectively receiving and storing data coupled to the latch circuit. A first enabling circuit responsive to the mode select signals enables the hold circuit to receive all the data contained in the array during a full write mode, and further enables the hold circuit to receive only some of the data bits contained in the array during a partial write mode.

Abstract: An apparatus and method are disclosed for detecting multiple hits in CAM arrays. A binary address value is stored for each entry of the CAM array and is output to identify the matching entry for a single hit. However, to facilitate multiple hit detection, both the true and complement components of this address are stored and output to determine whether or not a multiple hit occurred. If a multiple hit occurs (e.g., more than one address location has been matched), all the bits that make up the binary address and the complement will not be complements of each other and a multiple hit condition can be detected by XORing each bit of an address location value with the complement of that address location value. If the XORed bits are equal to “1”, then a single hit has occurred. Otherwise, a multiple hit has occurred.

Abstract: An apparatus and method is provided that combines both self test and functional features in a single latch circuit, which may be used with an SRAM array and is usefully embodied as an L1-L2 latch. During partial writes from an SRAM array, data bits of unknown state are inhibited from entering the latch circuit, while data for testing is allowed to enter. In one useful embodiment of the invention the latch circuit is used with a mode control that provides mode select signals to operate the latch circuit in one of a plurality of modes, including at least full write and partial write modes. The latch circuit further includes a data hold circuit for selectively receiving and storing data coupled to the latch circuit.

Abstract: An apparatus and method are disclosed for detecting multiple hits in CAM arrays. A binary address value is stored for each entry of the CAM array and is output to identify the matching entry for a single hit. However, to facilitate multiple hit detection, both the true and complement components of this address are stored and output to determine whether or not a multiple hit occurred. If a multiple hit occurs (e.g., more than one address location has been matched), all the bits that make up the binary address and the complement will not be complements of each other and a multiple hit condition can be detected by XORing each bit of an address location value with the complement of that address location value. If the XORed bits are equal to “1”, then a single hit has occurred. Otherwise, a multiple hit has occurred.