Abstract: A microprocessor including an instruction decoder for decoding a branch instruction to output a decoded result, a program counter, and a program counter controller for controlling the program counter on the basis of the decoded result. The program counter controller includes a first register for storing a first program counter value output from the instruction decoder. The program counter controller detects a coincidence of the first program counter value stored in the first register with a value of the program counter to set a second program counter value indicating a branch target of the branch instruction into the program counter.

Abstract: A microprocessor executes delayed instructions in which decoded results obtained at the instruction decoder unit 2 are stored in the ALU 361, the multiplier 363, the PC controller 365, the memory controller 367, and the shifter 369, and a program counter value related to a delayed value specified by a delayed instruction is stored into registers 362B, 364B, 366B and 370B.

Abstract: A microprocessor having a saturation operation unit comprising a decoder 220 for decoding a 4-bit saturation operation bit length data item into a 16-bit value, a decoder 221 for decoding a 5-bit saturation operation bit length data item into 1 to a 32-bit value, selectors 236, 237, 238, 239 and an operation unit 250 for outputting values stored in the decoder 220 and 221 or values obtained by inverting the values, per bit, stored in the decoder 220 and 221 when a target saturation operation value is over a saturated value detected by using selectors 234, 235 and operation units 226 and 227.

Abstract: A microprocessor executes delayed instructions in which decoded results obtained at the instruction decoder unit 2 are stored in the ALU 361, the multiplier 363, the PC controller 365, the memory controller 367, and the shifter 369, and a program counter value related to a delayed value specified by a delayed instruction is stored into registers 362B, 364B, 366B and 370B.