Abstract: A distributed digital cross-connect system (10) is provided. The system includes two or more network interface islands (12) that connect to the telecommunications network. The system (10) also includes one or more distributed services nodes (18). Each distributed services node (18) connects to two or more of the network interface islands (12). The network interface islands (12) can transmit data to each other through the distributed services node (18). An administration system (14) is also connected to each distributed services node (18) and each network interface island (12). The administration system (14) transmits matrix configuration and telecommunications channel routing data to the network interface islands (12) and the distributed services nodes (18).

Abstract: A timing system for distributing a timing signal includes a master timing system that receives a network timing reference. The master timing system generates a master timing signal from the network timing reference. A distributed services node timing system receives the master timing signal and embeds a timing signal into a data transmission frame. A network interface island receives the data transmission frame and retrieves the embedded timing signal therefrom.

Abstract: A distributed digital cross-connect system (10) is provided. The system includes two or more network interface islands (12) that connect to the telecommunications network. The system (10) also includes one or more distributed services nodes (18). Each distributed services node (18) connects to two or more of the network interface islands (12). The network interface islands (12) can transmit data to each other through the distributed services node (18). An administration system (14) is also connected to each distributed services node (18) and each network interface island (12). The administration system (14) transmits matrix configuration and telecommunications channel routing data to the network interface islands (12) and the distributed services nodes (18).

Abstract: A distributed digital switching system is provided that includes a plurality of service controllers (20) which are interconnected to each other through a network (10). A network arbitrator is provided that controls the flow of traffic on the network (10). Each of the service controllers (20) is operable to provide a switching configuration between inbound data to the service controller (20) and network terminations associated with each of the service controllers (20). A processor (150) on each of the service controllers (20) controls the operations thereof with the voice information stored in a memory (208) which can be configured with a circuit (204). Each of the service controllers (20) has associated therewith a conference circuit for defining and creating a conference that can access all inbound data and provide interconnections therebetween and output this on a single outbound conference channel. There can be multiple conferences created at each service controller (20).

Abstract: A timing system (100) for coordinating the components of a distributed digital cross-connect system (10) is provided. The timing system (100) includes a master timing system (102) that receives a network timing reference (98, 99) and generates a master timing signal. A distributed services node timing system (104, 106) is connected to the master timing system (102) and receives the master timing signal. The distributed services node timing system (104, 106) then embeds a timing signal in a data transmission frame (150). Two or more digital cross-connect timing systems (108) are connected to the distributed services node timing system (104, 106) and receive the data transmission frame (150). The digital cross-connect timing systems (108) retrieve the embedded timing signal from the data transmission frame (150).

Abstract: A message transport network (10) is provided for high speed switching between processing elements (72, 80). Clusters of low speed processing elements (72) may be connected to the message transport network (10) through a transport node controller (78). The transport node controller (78) and the high speed processors (80) are connected to the gateways (82). A pair of gateways (82) may be connected through a transport interchange node (106) to allow communication between processors (72, 80) associated with the gateways (82). A transport interchange supervisor (98) maintains a record of the status of each gateway (82) and generates commands to form connection between gateways (82) in the transport interchange node (106). A maintenance controller (102) and system maintenance processor (76) oversee the validity of the data being passed through the system on paths independent of the data transfer paths.

Abstract: A message transport network (10) is provided for high speed switching between processing elements (72, 80). Clusters of low speed processing elements (72) may be connected to the message transport network (10) through a transport node controller (78). The transport node controller (78) and the high speed processors (80) are connected to the gateways (82). A pair of gateways (82) may be connected through a transport interchange node (106) to allow communication between processors (72, 80) associated with the gateways (82). A transport interchange supervisor (98) maintains a record of the status of each gateway (82) and generates commands to form connection between gateways (82) in the transport interchange node (106). A maintenance controller (102) and system maintenance processor (76) oversee the validity of the data being passed through the system on paths independent of the data transfer paths.

Abstract: An interface apparatus, which interfaces a communication device to a highway wherein the highway includes a clock line, a data line, and a busy line, comprises a counter element which counts a clock signal transmitted on the clock line to generate a clock value. The counter includes a second input terminal connected to the busy line to disable the counting when a busy signal is present on the busy line. A compare element compares the clock value to a device number value associated with the communication device, each communication device coupled to the highway having a unique device number value, and outputs an enable signal when the clock value and the device number value are equal. A driver element permits data to be transmitted onto the data line in response to the enable signal when the communication device has data to be transmitted.

Abstract: The present invention relates to an apparatus for verifying a data path through a digital switch between a transmitting port and a receiving port. The apparatus comprises a transmitter which transmits a test data block in a first predetermined time slot which corresponds to the time slot associated with the transmitting port. A receiver receives the test data block in a second predetermined time slot, which corresponds to the time slot associated with the receiving port. Test logic examines the received test data block to determine that the test data block has been transmitted error-free through the digital switch thereby verifying the data path.

Abstract: The redundant digital switch matrix system of the present invention includes a plurality of primary digital switch elements, and incorporates a standby digital switch which can be substituted for any one of the plurality of primary digital switch elements in response to at least one select control signal.