Patents by Inventor Edgar R. Zuniga
Edgar R. Zuniga has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8648430Abstract: A semiconductor-centered MEMS device (100) integrates the movable microelectromechanical parts, such as mechanical elements, flexible membranes, and sensors, with the low-cost device package, and leaving only the electronics and signal-processing parts in the integrated circuitry of the semiconductor chip. The package is substrate-based and has an opening through the thickness of the substrate. Substrate materials include polymer tapes with attached metal foil, and polymer-based and ceramic-based multi-metal-layer dielectric composites with attached metal foil. The movable part is formed from the metal foil attached to a substrate surface and extends at least partially across the opening. The chip is flip-assembled to span at least partially across the membrane, and is separated from the membrane by a gap.Type: GrantFiled: November 6, 2012Date of Patent: February 11, 2014Assignee: Texas Instruments IncorporatedInventors: Edgar R. Zuniga-Ortiz, William R. Krenik
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Patent number: 7910471Abstract: A semiconductor chip having a planar active surface including an integrated circuit; the circuit has metallization patterns including a plurality of contact pads. Each of these contact pads has an added conductive layer on the circuit metallization. This added layer has a conformal surface adjacent the chip and a planar outer surface, and this outer surface is suitable to form metallurgical bonds without melting. The chip contact pads may have a distribution such that an area portion of the active chip surface is available for attaching a thermally conductive plate; this plate has a thickness compatible with the thickness of the conductive pad layer.Type: GrantFiled: February 2, 2004Date of Patent: March 22, 2011Assignee: Texas Instruments IncorporatedInventors: Edgar R. Zuniga-Ortiz, Sreenivasan K. Koduri
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Patent number: 7368328Abstract: A semiconductor device having a leadframe comprised of a base metal (110, e.g., copper), a chip mount pad (103) and a plurality of lead segments (104). Each of the segments has a first end (104a) near the mount pad and a second end (104b) remote from the mount pad. The device further has a semiconductor chip (103) attached to the mount pad and electrical interconnections (107) between the chip and the first segment ends. Encapsulation material (120) covers the chip, the bonding wires and the first segment ends, yet leaves the second segment ends exposed. At least portions of the second segment ends have the base metal covered by a layer of solderable metal (130, e.g., nickel) and by an outermost layer of noble metal (140, e.g., stack of palladium and gold).Type: GrantFiled: August 1, 2007Date of Patent: May 6, 2008Assignee: Texas Instruments IncorporatedInventors: Donald C Abbott, Edgar R Zuniga-Ortiz
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Patent number: 7268415Abstract: A semiconductor device having a leadframe comprised of a base metal (110, e.g., copper), a chip mount pad (103) and a plurality of lead segments (104). Each of the segments has a first end (104a) near the mount pad and a second end (104b) remote from the mount pad. The device further has a semiconductor chip (103) attached to the mount pad and electrical interconnections (107) between the chip and the first segment ends. Encapsulation material (120) covers the chip, the bonding wires and the first segment ends, yet leaves the second segment ends exposed. At least portions of the second segment ends have the base metal covered by a layer of solderable metal (130, e.g., nickel) and by an outermost layer of noble metal (140, e.g., stack of palladium and gold).Type: GrantFiled: November 9, 2004Date of Patent: September 11, 2007Assignee: Texas Instruments IncorporatedInventors: Donald C. Abbott, Edgar R. Zuniga-Ortiz
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Patent number: 6914332Abstract: A semiconductor chip having a planar active surface including an integrated circuit protected by an inorganic overcoat; the circuit has metallization patterns including a plurality of contact pads. Each of these contact pads has an added conductive layer on the circuit metallization. This added layer has a conformal surface adjacent the chip, including peripheral portions of the overcoat, and a planar outer surface; this outer surface is suitable to form metallurgical bonds without melting. The chip contact pads may have a distribution arrayed in the center of the chip in close proximity to the chip neutral line; the distribution may leave an area portion of the active chip surface available for attaching a thermally conductive plate. The chip may further have a non-conductive adhesive layer over the overcoat, filling the spaces between the added conductive layers on each contact pad.Type: GrantFiled: January 25, 2002Date of Patent: July 5, 2005Assignee: Texas Instruments IncorporatedInventors: Edgar R. Zuniga-Ortiz, Sreenivasan K. Koduri
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Publication number: 20040227216Abstract: Disclosed are flex resistant die pads (18), leadframes (16), and high aspect ratio semiconductor packages (10) using the same. Methods for making devices (10, 16, and 18) according to the invention are also disclosed. Preferred embodiments of the invention are described in which tie bars (24) extending outward from the attachment region (20) of a die pad (18) are used to increase flex resistance of die pads (18), leadframes (16), and packages (10).Type: ApplicationFiled: February 2, 2004Publication date: November 18, 2004Inventors: Robert F. Mortan, Lance Wright, Edgar R. Zuniga
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Patent number: 6768210Abstract: A semiconductor chip having a planar active surface including an integrated circuit; the circuit has metallization patterns including a plurality of contact pads. Each of these contact pads has an added conductive layer on the circuit metallization. This added layer has a conformal surface adjacent the chip and a planar outer surface, and this outer surface is suitable to form metallurgical bonds without melting. The chip contact pads may have a distribution such that an area portion of the active chip surface is available for attaching a thermally conductive plate; this plate has a thickness compatible with the thickness of the conductive pad layer.Type: GrantFiled: November 1, 2001Date of Patent: July 27, 2004Assignee: Texas Instruments IncorporatedInventors: Edgar R. Zuniga-Ortiz, Sreenivasan K. Koduri
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Publication number: 20030141593Abstract: A semiconductor chip having a planar active surface including an integrated circuit protected by an inorganic overcoat; the circuit has metallization patterns including a plurality of contact pads. Each of these contact pads has an added conductive layer on the circuit metallization. This added layer has a conformal surface adjacent the chip, including peripheral portions of the overcoat, and a planar outer surface; this outer surface is suitable to form metallurgical bonds without melting. The chip contact pads may have a distribution arrayed in the center of the chip in close proximity to the chip neutral line; the distribution may leave an area portion of the active chip surface available for attaching a thermally conductive plate. The chip may further have a non-conductive adhesive layer over the overcoat, filling the spaces between the added conductive layers on each contact pad.Type: ApplicationFiled: January 25, 2002Publication date: July 31, 2003Inventors: Edgar R. Zuniga-Ortiz, Sreenivasan K. Koduri
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Publication number: 20030080392Abstract: A semiconductor chip having a planar active surface including an integrated circuit; the circuit has metallization patterns including a plurality of contact pads. Each of these contact pads has an added conductive layer on the circuit metallization. This added layer has a conformal surface adjacent the chip and a planar outer surface, and this outer surface is suitable to form metallurgical bonds without melting. The chip contact pads may have a distribution such that an area portion of the active chip surface is available for attaching a thermally conductive plate; this plate has a thickness compatible with the thickness of the conductive pad layer.Type: ApplicationFiled: November 1, 2001Publication date: May 1, 2003Inventors: Edgar R. Zuniga-Ortiz, Sreenivasan K. Koduri
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Patent number: 6384486Abstract: An architecture and method of fabrication for an integrated circuit 200 having a bond pad 208; at least one portion of said integrated circuit disposed under said contact pad and electrically connected to said pad through a via 205; a combination of a bondable metal layer 207, a stress-absorbing metal layer 203, and a mechanically strengthened, electrically insulating layer 204; and said combination of layers separating said contact pad and said portion of said integrated circuit, and having sufficient thickness to protect said circuit from bonding impact.Type: GrantFiled: December 10, 1999Date of Patent: May 7, 2002Assignee: Texas Instruments IncorporatedInventors: Edgar R. Zuniga, Samuel A. Ciani
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Publication number: 20020000671Abstract: An architecture and method of fabrication for an integrated circuit having a bond pad; at lest one portion of said integrated circuit disposed under said contact pad and electrically connected to said pad through a via; a combination of a bondable metal layer, a stress-absorbing metal layer, and a mechanically strengthened, electrically insulating layer; and said combination of layers separating said contact pad and said portion of said integrated circuit, and having sufficient thickness to protect said circuit from bonding impact.Type: ApplicationFiled: December 10, 1999Publication date: January 3, 2002Inventors: EDGAR R. ZUNIGA, SAMUEL A. CIANI
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Patent number: 5939777Abstract: An integrated circuit chip package (10) including a high aspect ratio integrated circuit chip (12) is disclosed. The chip (12) has a length (L1) than is greater than three times its width (L2). The chip includes a plurality of circuit functional blocks (14), each having a plurality of integrated circuit components and bond pads (16) for the input and output of signals. In one embodiment, the circuit functional blocks (14) are aligned in parallel to form a row of circuit functional blocks. The high aspect ratio integrated circuit chip (12) requires less wafer area than a comparable low aspect ratio chip, thus allowing more chips to be made from a single semiconductor wafer at a lower cost per chip. Moreover, the disclosed method for producing a high aspect ratio integrated circuit chip package (10) minimizes the risk of cracking the high aspect ratio integrated circuit chip (12) during the packaging process.Type: GrantFiled: December 5, 1997Date of Patent: August 17, 1999Assignee: Texas Instruments IncorporatedInventor: Edgar R. Zuniga
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Patent number: 5837558Abstract: An improved method for packaging an integrated circuit chip is disclosed. In accordance with the invention, an integrated circuit chip (12) is mounted on a leadframe (18) having a plurality of leads (20). The integrated circuit chip is electrically connected to the leadframe with wire bonds (22). An encapsulant (26) is then molded around the integrated circuit chip and the leadframe. In a dry bake step, moisture is removed from the encapsulant (26) for dry shipment of the integrated circuit chip subsequent to the molding step. The encapsulant (26) is cured simultaneously with the dry bake step, thus reducing the time and power required to produce the integrated circuit chip package.Type: GrantFiled: November 4, 1997Date of Patent: November 17, 1998Assignee: Texas Instruments IncorporatedInventors: Edgar R. Zuniga, Mary E. Helmick
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Patent number: 5664497Abstract: The invention is to a method of placing symbolization on a heat spreader, used in conjunction with the semiconductor package, through the use of a low powered laser beam. The beam is scanned over the package surface at a preset intensity and for a desired time to change the surface texture of the heat spreader, and to change the reflectivity of the scanned area.Type: GrantFiled: December 20, 1995Date of Patent: September 9, 1997Assignee: Texas Instruments IncorporatedInventors: Edgar R. Zuniga, Archie W. Sutton, Ray H. Purdom