Patents by Inventor Edgard FIALLOS

Edgard FIALLOS has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230422095
    Abstract: Embodiments include methods for scheduling processing resources for physical layer, (PHY) communications in a wireless network. Such methods include estimating processing resources needed, during a subsequent second duration, for PHY communications in one or more cells of the wireless network, based on: a first transmission timing configuration for the one or more cells, current workload of radio units, RUs, serving the one or more cells, and information about user data traffic scheduled for transmission or reception in the one or more cells during a first duration. The first duration can precede the second duration by at least a scheduling delay associated with the processing resources. Such methods include sending, to a resource management function, a request for the estimated processing resources during the second duration. Other embodiments include processing systems, wireless networks, PHY task resource schedulers (TRS), computer-readable media, and computer program products embodying such methods.
    Type: Application
    Filed: November 30, 2020
    Publication date: December 28, 2023
    Inventors: Johan Eker, Edgard Fiallos
  • Patent number: 11856079
    Abstract: Apparatuses and methods are disclosed for optimizing an L2-L1 interface. In some embodiments, a method for a network node includes grouping, at an open systems interconnection, OSI, layer 2, L2, codeblocks, CBs, based at least in part on a hardware property associated with an OSI layer 1, L1, processing engine; and sending the grouped CBs to the OSI L1 processing engine. In some embodiments, a method for a network node includes receiving, by an open systems interconnection, OSI, layer 1, L1, processing engine, a group of codeblocks, CBs, the CBs being grouped together based at least in part on a hardware property associated with the OSI L1 processing engine; and performing CB group-level encoding on at least the received group of CBs.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: December 26, 2023
    Assignee: TELEFONAKTIEBOLAGET LM ERICSSON (PUBL)
    Inventors: Christophe Milard, Edgard Fiallos
  • Publication number: 20220311841
    Abstract: Apparatuses and methods are disclosed for optimizing an L2-L1 interface. In some embodiments, a method for a network node includes grouping, at an open systems interconnection, OSI, layer 2, L2, codeblocks, CBs, based at least in part on a hardware property associated with an OSI layer 1, L1, processing engine; and sending the grouped CBs to the OSI L1 processing engine. In some embodiments, a method for a network node includes receiving, by an open systems interconnection, OSI, layer 1, L1, processing engine, a group of codeblocks, CBs, the CBs being grouped together based at least in part on a hardware property associated with the OSI L1 processing engine; and performing CB group-level encoding on at least the received group of CBs.
    Type: Application
    Filed: June 28, 2019
    Publication date: September 29, 2022
    Inventors: Christophe MILARD, Edgard FIALLOS
  • Publication number: 20210382745
    Abstract: Example methods and apparatus disclosed herein use the “processing margin” at a radio unit (RU) (24) as a control variable for modifying the allocation of virtualized processing resources used by a digital unit (DU) (16) that supports the RU (24). The DU (16) and RU (24) form a radio processing chain with a functional split, in which the DU (16) performs certain processing operations and provides corresponding processed data to the RU (24), which performs further processing for the generation and transmission of the corresponding radio signals. The “slack” between the end of processing in the RU (24) and the corresponding required transmission time represents the processing margin. The processing-margin feedback loop allows for the virtualization of all or part the DU (16), while avoiding the need for the network operator to implement or pay for over-dimensioning of the DU (16), as would be needed to ensure that a static resource allocation meets worst-case processing needs.
    Type: Application
    Filed: September 26, 2018
    Publication date: December 9, 2021
    Inventors: Johan Eker, Edgard Fiallos
  • Patent number: 9629151
    Abstract: A method and system for managing a transmission buffer memory at a base station in a wireless communication system, the base station having a plurality of cells, the memory being circular and shared among the cells so that memory fragmentation when cells are removed or added is avoided.
    Type: Grant
    Filed: March 30, 2015
    Date of Patent: April 18, 2017
    Assignee: TELEFONAKTIEBOLAGET LM ERICSSON (PUBL)
    Inventors: Edgard Fiallos, Christien LeBlanc
  • Publication number: 20170048849
    Abstract: A method and system for managing a transmission buffer memory at a base station in a wireless communication system, the base station having a plurality of cells, the memory being circular and shared among the cells so that memory fragmentation when cells are removed or added is avoided.
    Type: Application
    Filed: March 30, 2015
    Publication date: February 16, 2017
    Inventors: Edgard FIALLOS, Christien LEBLANC
  • Patent number: 9312994
    Abstract: A downlink physical layer processing system includes a transport block segmentation processor that receives a transport block and generates segmented blocks from the transport block, an encoder that encodes the segmented blocks and forms encoded blocks, a mapping processor that maps the encoded blocks to symbols corresponding to resource elements to generate mapped symbols for transmission over a transmission medium, and a transmission signal generator that processes the mapped symbols to generate transmission signals for transmission over the transmission medium. The mapping processor maps the encoded blocks to the symbols in response to a control signal generated by the transmission signal generator. The encoder thereby operates in response to timing of data received by the encoder while the mapping processor operates in response to timing of processing of symbols by the transmission signal generator.
    Type: Grant
    Filed: September 30, 2013
    Date of Patent: April 12, 2016
    Assignee: Telefonaktiebolaget LM Ericsson (publ)
    Inventors: Edgard Fiallos, Christien Leblanc, Johan Eker
  • Publication number: 20150092671
    Abstract: A downlink physical layer processing system includes a transport block segmentation processor that receives a transport block and generates segmented blocks from the transport block, an encoder that encodes the segmented blocks and forms encoded blocks, a mapping processor that maps the encoded blocks to symbols corresponding to resource elements to generate mapped symbols for transmission over a transmission medium, and a transmission signal generator that processes the mapped symbols to generate transmission signals for transmission over the transmission medium. The mapping processor maps the encoded blocks to the symbols in response to a control signal generated by the transmission signal generator. The encoder thereby operates in response to timing of data received by the encoder while the mapping processor operates in response to timing of processing of symbols by the transmission signal generator.
    Type: Application
    Filed: September 30, 2013
    Publication date: April 2, 2015
    Applicant: Telefonaktiebolaget L M Ericsson (publ)
    Inventors: Edgard FIALLOS, Christien LEBLANC, Johan EKER