Patents by Inventor Edgardo Laber
Edgardo Laber has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 10782355Abstract: Systems and methods for an open wire scan are provided. In certain embodiments, An apparatus comprising a circuit includes a plurality of inputs for connecting with a plurality of outputs of a multi-cell battery pack; and an open connection detection circuit, formed within the circuit, for detecting an open connection on at least one of the plurality of inputs connected to the multi-cell battery pack and generating a fault condition responsive thereto. The open connection detection circuit comprises at least one current source device; and at least one device for turning on and off the at least one current source device. The open connection detection circuit also comprises at least one amplifier; an analog to digital converter; and a control logic circuit.Type: GrantFiled: October 16, 2018Date of Patent: September 22, 2020Assignee: Intersil Americas LLCInventors: Anthony John Allen, Edgardo A. Laber
-
Publication number: 20190056454Abstract: Systems and methods for an open wire scan are provided. In certain embodiments, An apparatus comprising a circuit includes a plurality of inputs for connecting with a plurality of outputs of a multi-cell battery pack; and an open connection detection circuit, formed within the circuit, for detecting an open connection on at least one of the plurality of inputs connected to the multi-cell battery pack and generating a fault condition responsive thereto. The open connection detection circuit comprises at least one current source device; and at least one device for turning on and off the at least one current source device. The open connection detection circuit also comprises at least one amplifier; an analog to digital converter; and a control logic circuit.Type: ApplicationFiled: October 16, 2018Publication date: February 21, 2019Applicant: INTERSIL AMERICAS LLCInventors: Anthony John Allen, Edgardo A. Laber
-
Patent number: 10101403Abstract: Systems and methods for an open wire scan are provided. In certain embodiments, An apparatus comprising a circuit includes a plurality of inputs for connecting with a plurality of outputs of a multi-cell battery pack; and an open connection detection circuit, formed within the circuit, for detecting an open connection on at least one of the plurality of inputs connected to the multi-cell battery pack and generating a fault condition responsive thereto. The open connection detection circuit comprises at least one current source device; and at least one device for turning on and off the at least one current source device. The open connection detection circuit also comprises at least one amplifier; an analog to digital converter; and a control logic circuit.Type: GrantFiled: November 25, 2014Date of Patent: October 16, 2018Assignee: INTERSIL AMERICAS LLCInventors: Anthony John Allen, Edgardo A. Laber
-
Publication number: 20160003914Abstract: Systems and methods for an open wire scan are provided. In certain embodiments, An apparatus comprising a circuit includes a plurality of inputs for connecting with a plurality of outputs of a multi-cell battery pack; and an open connection detection circuit, formed within the circuit, for detecting an open connection on at least one of the plurality of inputs connected to the multi-cell battery pack and generating a fault condition responsive thereto. The open connection detection circuit comprises at least one current source device; and at least one device for turning on and off the at least one current source device. The open connection detection circuit also comprises at least one amplifier; an analog to digital converter; and a control logic circuit.Type: ApplicationFiled: November 25, 2014Publication date: January 7, 2016Inventors: Anthony John Allen, Edgardo A. Laber
-
Patent number: 8797043Abstract: An apparatus comprises an integrated circuit and an open connection detection circuit within the integrated circuit. The integrated circuit includes a plurality of inputs for connecting with a plurality of outputs of a multi-cell battery pack. The open connection detection circuit within the integrated circuit detects an open connection on at least one of the plurality of inputs from the multi-cell battery and generates a fault condition responsive thereto.Type: GrantFiled: June 30, 2011Date of Patent: August 5, 2014Assignee: Intersil Americas Inc.Inventors: Edgardo Laber, Anthony Allen, Carlos Martinez
-
Patent number: 8345488Abstract: A flash memory array comprises a plurality of memory cells organized in a matrix of rows and columns. Each of the memory cells includes a floating gate memory transistor having a source region and a drain region, and a coupling capacitor electrically connected to the memory transistor. A plurality of word lines are each electrically connected to the capacitor in each of the memory cells in a respective row. A first set of bit lines are each electrically connected to the drain region of the memory transistor in each of the memory cells in a respective column. A plurality of high voltage access transistors are each electrically connected to a bit line in the first set of bit lines. A second set of bit lines are each electrically connected to the source region of the memory transistor in each of the memory cells in a respective column.Type: GrantFiled: April 6, 2011Date of Patent: January 1, 2013Assignee: Intersil Americas Inc.Inventors: Hosam Haggag, Alexander Kalnitsky, Edgardo Laber, Prabhjot Singh, Michael D. Church
-
Patent number: 8325522Abstract: A memory array comprises a plurality of memory cells organized in a matrix of rows and columns. Each of the memory cells includes a high voltage access transistor, a floating gate memory transistor electrically connected to the access transistor, and a coupling capacitor electrically connected to the memory transistor. A first set of word lines are each electrically connected to the capacitor in each of the memory cells in a respective row. A second set of word lines are each electrically connected to the access transistor in each of the memory cells in a respective row. A first set of bit lines are each electrically connected to the access transistor in each of the memory cells in a respective column. A second set of bit lines are each electrically connected to the memory transistor in each of the memory cells in a respective column.Type: GrantFiled: January 24, 2011Date of Patent: December 4, 2012Assignee: Intersil Americas Inc.Inventors: Hosam Haggag, Alexander Kalnitsky, Edgardo Laber, Michael D. Church, Yun Yue
-
Patent number: 8315100Abstract: A memory array comprises a plurality of memory cells organized in a matrix of rows and columns. Each of the memory cells includes a high voltage access transistor, a floating gate memory transistor electrically connected to the access transistor, and a coupling capacitor electrically connected to the memory transistor. A first set of word lines are each electrically connected to the capacitor in each of the memory cells in a respective row. A second set of word lines are each electrically connected to the access transistor in each of the memory cells in a respective row. A first set of bit lines are each electrically connected to the access transistor in each of the memory cells in a respective column. A second set of bit lines are each electrically connected to the memory transistor in each of the memory cells in a respective column.Type: GrantFiled: January 24, 2011Date of Patent: November 20, 2012Assignee: Intersil Americas Inc.Inventors: Hosam Haggag, Alexander Kalnitsky, Edgardo Laber, Michael D. Church, Yun Yue
-
Patent number: 8218370Abstract: A memory array comprises a plurality of memory cells organized in a matrix of rows and columns. Each of the memory cells includes a high voltage access transistor, a floating gate memory transistor electrically connected to the access transistor, and a coupling capacitor electrically connected to the memory transistor. A first set of word lines are each electrically connected to the capacitor in each of the memory cells in a respective row. A second set of word lines are each electrically connected to the access transistor in each of the memory cells in a respective row. A first set of bit lines are each electrically connected to the access transistor in each of the memory cells in a respective column. A second set of bit lines are each electrically connected to the memory transistor in each of the memory cells in a respective column.Type: GrantFiled: January 24, 2011Date of Patent: July 10, 2012Assignee: Intersil Americas Inc.Inventors: Hosam Haggag, Alexander Kalnitsky, Edgardo Laber, Michael D. Church, Yun Yue
-
Publication number: 20120086401Abstract: An apparatus for balancing a multi-cell battery pack has a plurality of switchable loads. Each of the plurality of switchable loads are associated with one of a plurality of cells of a multi-cell battery. The plurality of switchable loads discharge an associated cell in a first mode and diverts part of a charging current away from the associated cell in a second mode responsive to a drive signal. A plurality of current mode driver circuits applies the drive signal to each of the plurality of switched loads.Type: ApplicationFiled: May 9, 2011Publication date: April 12, 2012Applicant: INTERSIL AMERICAS INC.Inventors: EDGARDO LABER, ANTHONY ALLEN, CARLOS MARTINEZ
-
Publication number: 20120081128Abstract: An apparatus comprises an integrated circuit and an open connection detection circuit within the integrated circuit. The integrated circuit includes a plurality of inputs for connecting with a plurality of outputs of a multi-cell battery pack. The open connection detection circuit within the integrated circuit detects an open connection on at least one of the plurality of inputs from the multi-cell battery and generates a fault condition responsive thereto.Type: ApplicationFiled: June 30, 2011Publication date: April 5, 2012Applicant: INTERSIL AMERICAS INC.Inventors: EDGARDO LABER, ANTHONY ALLEN, CARLOS MARTINEZ
-
Publication number: 20110182126Abstract: A flash memory array comprises a plurality of memory cells organized in a matrix of rows and columns. Each of the memory cells includes a floating gate memory transistor having a source region and a drain region, and a coupling capacitor electrically connected to the memory transistor. A plurality of word lines are each electrically connected to the capacitor in each of the memory cells in a respective row. A first set of bit lines are each electrically connected to the drain region of the memory transistor in each of the memory cells in a respective column. A plurality of high voltage access transistors are each electrically connected to a bit line in the first set of bit lines. A second set of bit lines are each electrically connected to the source region of the memory transistor in each of the memory cells in a respective column.Type: ApplicationFiled: April 6, 2011Publication date: July 28, 2011Applicant: INTERSIL AMERICAS INC.Inventors: Hosam Haggag, Alexander Kalnitsky, Edgardo Laber, Prabhjot Singh, Michael D. Church
-
Publication number: 20110116324Abstract: A memory array comprises a plurality of memory cells organized in a matrix of rows and columns. Each of the memory cells includes a high voltage access transistor, a floating gate memory transistor electrically connected to the access transistor, and a coupling capacitor electrically connected to the memory transistor. A first set of word lines are each electrically connected to the capacitor in each of the memory cells in a respective row. A second set of word lines are each electrically connected to the access transistor in each of the memory cells in a respective row. A first set of bit lines are each electrically connected to the access transistor in each of the memory cells in a respective column. A second set of bit lines are each electrically connected to the memory transistor in each of the memory cells in a respective column.Type: ApplicationFiled: January 24, 2011Publication date: May 19, 2011Applicant: INTERSIL AMERICAS INC.Inventors: Hosam Haggag, Alexander Kalnitsky, Edgardo Laber, Michael D. Church, Yun Yue
-
Publication number: 20110116319Abstract: A memory array comprises a plurality of memory cells organized in a matrix of rows and columns. Each of the memory cells includes a high voltage access transistor, a floating gate memory transistor electrically connected to the access transistor, and a coupling capacitor electrically connected to the memory transistor. A first set of word lines are each electrically connected to the capacitor in each of the memory cells in a respective row. A second set of word lines are each electrically connected to the access transistor in each of the memory cells in a respective row. A first set of bit lines are each electrically connected to the access transistor in each of the memory cells in a respective column. A second set of bit lines are each electrically connected to the memory transistor in each of the memory cells in a respective column.Type: ApplicationFiled: January 24, 2011Publication date: May 19, 2011Applicant: INTERSIL AMERICAS INC.Inventors: Hosam Haggag, Alexander Kalnitsky, Edgardo Laber, Michael D. Church, Yun Yue
-
Publication number: 20110116318Abstract: A memory array comprises a plurality of memory cells organized in a matrix of rows and columns. Each of the memory cells includes a high voltage access transistor, a floating gate memory transistor electrically connected to the access transistor, and a coupling capacitor electrically connected to the memory transistor. A first set of word lines are each electrically connected to the capacitor in each of the memory cells in a respective row. A second set of word lines are each electrically connected to the access transistor in each of the memory cells in a respective row. A first set of bit lines are each electrically connected to the access transistor in each of the memory cells in a respective column. A second set of bit lines are each electrically connected to the memory transistor in each of the memory cells in a respective column.Type: ApplicationFiled: January 24, 2011Publication date: May 19, 2011Applicant: INTERSIL AMERICAS INC.Inventors: Hosam Haggag, Alexander Kalnitsky, Edgardo Laber, Michael D. Church, Yun Yue
-
Patent number: 7944745Abstract: A flash memory array comprises a plurality of memory cells organized in a matrix of rows and columns. Each of the memory cells includes a floating gate memory transistor having a source region and a drain region, and a coupling capacitor electrically connected to the memory transistor. A plurality of word lines are each electrically connected to the capacitor in each of the memory cells in a respective row. A first set of bit lines are each electrically connected to the drain region of the memory transistor in each of the memory cells in a respective column. A plurality of high voltage access transistors are each electrically connected to a bit line in the first set of bit lines. A second set of bit lines are each electrically connected to the source region of the memory transistor in each of the memory cells in a respective column.Type: GrantFiled: February 24, 2010Date of Patent: May 17, 2011Assignee: Intersil Americas Inc.Inventors: Hosam Haggag, Alexander Kalnitsky, Edgardo Laber, Prabhjot Singh, Michael D. Church
-
Patent number: 7903465Abstract: A memory array comprises a plurality of memory cells organized in a matrix of rows and columns. Each of the memory cells includes a high voltage access transistor, a floating gate memory transistor electrically connected to the access transistor, and a coupling capacitor electrically connected to the memory transistor. A first set of word lines are each electrically connected to the capacitor in each of the memory cells in a respective row. A second set of word lines are each electrically connected to the access transistor in each of the memory cells in a respective row. A first set of bit lines are each electrically connected to the access transistor in each of the memory cells in a respective column. A second set of bit lines are each electrically connected to the memory transistor in each of the memory cells in a respective column.Type: GrantFiled: September 25, 2007Date of Patent: March 8, 2011Assignee: Intersil Americas Inc.Inventors: Hosam Haggag, Alexander Kalnitsky, Edgardo Laber, Michael D. Church, Yun Yue
-
Publication number: 20100149879Abstract: A flash memory array comprises a plurality of memory cells organized in a matrix of rows and columns. Each of the memory cells includes a floating gate memory transistor having a source region and a drain region, and a coupling capacitor electrically connected to the memory transistor. A plurality of word lines are each electrically connected to the capacitor in each of the memory cells in a respective row. A first set of bit lines are each electrically connected to the drain region of the memory transistor in each of the memory cells in a respective column. A plurality of high voltage access transistors are each electrically connected to a bit line in the first set of bit lines. A second set of bit lines are each electrically connected to the source region of the memory transistor in each of the memory cells in a respective column.Type: ApplicationFiled: February 24, 2010Publication date: June 17, 2010Applicant: INTERSIL AMERICAS INC.Inventors: Hosam Haggag, Alexander Kalnitsky, Edgardo Laber, Prabhjot Singh, Michael D. Church
-
Patent number: 7688627Abstract: A flash memory array comprises a plurality of memory cells organized in a matrix of rows and columns. Each of the memory cells includes a floating gate memory transistor having a source region and a drain region, and a coupling capacitor electrically connected to the memory transistor. A plurality of word lines are each electrically connected to the capacitor in each of the memory cells in a respective row. A first set of bit lines are each electrically connected to the drain region of the memory transistor in each of the memory cells in a respective column. A plurality of high voltage access transistors are each electrically connected to a bit line in the first set of bit lines. A second set of bit lines are each electrically connected to the source region of the memory transistor in each of the memory cells in a respective column.Type: GrantFiled: September 25, 2007Date of Patent: March 30, 2010Assignee: Intersil Americas Inc.Inventors: Hosam Haggag, Alexander Kalnitsky, Edgardo Laber, Prabhjot Singh, Michael D. Church
-
Patent number: 7502264Abstract: Circuits, methods, and apparatus that provide waveforms having controlled rise and fall times, as well as accurate peak voltages. One embodiment provides circuitry for generating a clock signal and a current that are adjusted for an on-chip capacitance variation. This current is then used to generate rising and falling edges of a waveform. The clock signal is used to determine timing of transitions in the waveform. A bandgap or similar reference voltage is used to determine the peak voltage. This waveform is then gained using an amplifier circuit, and the output of the amplifier circuit is used as a programming voltage waveform for an EE-PROM. One embodiment further uses non-overlapping clocks to drive a charge pump that is used to generate a supply voltage for the amplifier circuit that far exceeds the available on-chip supply voltages.Type: GrantFiled: November 30, 2006Date of Patent: March 10, 2009Assignee: Intersil Americas Inc.Inventors: Bertram J. Rodgers, III, Edgardo A. Laber