Abstract: A look-ahead flag generator generates a flag signal corresponding to the occurrence of a predetermined value stored in a counter (10). The output of the counter outputs any of a plurality of values, the values including the predetermined value and at least one boundary value that is one unit of increment or decrement displaced from the predetermined value. A clock signal source (13) is coupled to a first input of the counter (10) to indicate a decrement or an increment to the value stored in the counter (10). An up/down signal source (11) is coupled to a second input of the counter to indicate whether an increment or a decrement of the stored value should be performed. Predetermined states of the up/down signal and the clock signal are operable to cause a boundary value stored in the counter (10) to be changed to the predetermined value. A predecoder (12) is coupled to an output of counter (10) for decoding the boundary value. A latch (132) stores the decoded boundary value.

Abstract: An arbiter (52) is operable to supply an up/down signal (11) and a clock signal (13) to an up/down counter (10) so that the up/down counter (10) can count the difference between read requests (54) and write requests (56) experienced by an associated FIFO memory.The arbiter (52) is operable to receive asynchronous read and write requests (54, 56) that are closely spaced in time or appear simultaneously, and to store the read request in a read latch (104) and the write request in a write latch (92). A decision circuit (62) is operable to determine priority between the read and write requests, and processes the request that is awarded priority. Once the first priority request has been processed, the stored non-priority request is then processed.

Abstract: An arbiter (52) is operable to supply an up/down signal (11) and a clock signal (13) to an up/down counter (10) so that the up/down counter (10) can count the difference between read requests (54) and write requests (56) experienced by an associated FIFO memory.The arbiter (52) is operable to receive asynchronous read and write requests (54, 56) that are closely spaced in time or appear simultaneously, and to store the read request in a read latch (104) and the write request in a write latch (92). A decision circuit (62) is operable to determine priority between the read and write requests, and processes the request that is awarded priority. Once the first priority request has been processed, the stored second non-priority request is then processed.