Abstract: A spatial light modulator (10) with a programmable format pixel array (14). The pixel array (14) has a programmable row address circuit (30), and a partitionable programmable column data loading circuit (32) which permits the array (14) to be operated in multiple formats compatible with NTSC, PAL, SECAM and other broadcasting standards. The pixel array (14) is of the DMD type. The array can be configured as 864.times.576 pixel array, a 768.times.576 pixel array, an 864.times.480 pixel array, or a 640.times.480 pixel array. This format is controlled by hardware (30,32) designed into the DMD chip. A partitionable shift register (32) has a MUXED input to provide testability, permitting some or all of the data input lines (D0-D53) to be utilized, and also allowing pixel data to be loaded back into the shift register (32) for functional verification. A programmable row address circuit (30) automatically addresses a subset of pixel rows as a function of a single input.

Abstract: A spatial light modulator (SLM) (20) having a pixel array (21) and a memory cell array (21a). Drivers (23c, 24b, 26, 27, 28) for the memory cell inputs permit pixels (10) of the SLM (20) to be addressed at a higher voltage than the voltage used for peripheral control circuitry (22, 23, 24). Each driver (23c, 24b, 26, 27, 28) has appropriate logic for providing an input signal to the memory cell array (21a) and a voltage translator (60) for changing the voltage level of that signal.

Abstract: A spatial light modulator (SLM) device (30) having a pixel array (31) and an associated memory cell array (36). Each memory cell (10a) receives pixel data from a single bit-line that carries pixel data down columns of the memory cell array (36). Each memory cell (10a) has two latches (21, 25). A first latch (21) receives data from the bit-line. A second latch (25) receives data transferred from the first latch (21) in response to a transfer signal, and is in electrical communication with at least one address electrode (14) of each pixel (10) of the pixel array (31).

Abstract: A spatial light modulator (10) of the DMD type having an array of memory cells (16) controlling an array of pixels (12). The memory cell array (16) has several integral, interleaved spare rows of memory cells MR (R1), MR (R2), and MR (R3), which can be selectively utilized to replace a defective row of primary memory cells. A fused row address mapping logic circuit (40) includes a network of fuses (F0-F12) and controls the implementation of memory cells, as well as the mapping of address signals to the memory cells as a function of inputs (R0-R11) received from a row decoder circuit (20). This circuit (40) is transparent to the row address decoder circuit (20). The present invention is suitable for large spatial light modulators compatible with high definition television (HDTV). High yield devices can be obtained with the present invention.

Abstract: A color palette is provided having a plurality input terminals for receiving a plurality of bits of data having an order. A two color path is included which comprises first circuitry coupled to the input terminals for selectively reversing the order of the plurality of bits of data. Second circuitry is coupled to the first circuitry and is operable in a first mode to pass all of the plurality of bits of data received from the first circuitry and in a second mode has at least one word comprising selected ones of the plurality of bits, the selected ones of the bits having a bit order. The third circuitry is provided coupled to the second circuitry and operable to pass all of the bits of data received from the second circuitry in the first mode and operable to selectively reverse the ordering of the selected ones of the bits and pass be at least one word received from the second circuitry in the second mode.

Abstract: A NAND gate circuit system that provides for adjustable pulse width that comprises eight transistors arranged so that a signal can propagate through the transistors in series, the transistors consisting of at least one N-channel and at least one P-channel transistor.

Abstract: A floating point processor (10) is provided having a multiplier (48) and an ALU (54) for performing arithmetic calculations simultaneously. The output of the multiplier (48) and ALU (54) are stored in a product register (64) and a sum register (66), respectively. Multiplexers (40,42,44,46) are provided at the inputs to the multiplier (48) and the ALU (54). The multiplexers choose between data in input registers (32,34), product and sum registers (64,66), and an output register (76). Since the multiplier (48) and ALU (54) operate simultaneously, and since the outputs of the multiplier (48) and ALU (54) are available to the multiplexers (40-46), product of sums calculations and sum of products calculations may be performed rapidly. An input stage (12) uses a temporary register (18) to store data from a data bus on the first clock edge, and configuration logic (28) for directing data from the data bus and the temporary register (18) to the input registers (32,34) on a second clock edge.

Abstract: A floating point processor (10) is provided having a multiplier (48) and an ALU (54) for performing arithmetic calculations simultaneously. The output of the multiplier (48) and ALU (54) are stored in a product register (64) and a sum register (66), respectively. Multiplexers (40,42,44,46) are provided at the inputs to the multiplier (48) and the ALU (54). The multiplexers choose between data in input registers (32,34), product and sum registers (64,66), and an output register (76). Since the multiplier (48) and ALU (54) operate simultaneously, and since the outputs of the multiplier (48) and ALU (54) are available to the multiplexers (40-46), product of sums calculations and sum of products calculations may be performed rapidly. An input stage (12) uses a temporary register (18) to store data from a data bus on the first clock edge, and configuration logic (28) for directing data from the data bus and the temporary register (18) to the input registers (32,34) on a second clock edge.

Abstract: The disclosure relates to a cache memory formed on a single chip wherein the ability to test the address comparator, cache memory diagnostics are improved, cache memory are capable of being read out. The architecture comprises a parity generator, a parity checker, a comparator and an SRAM memory call array. The cache memory is cascadable for access to an increased address range and to provide increased memory capacity.

Abstract: A circuit for resetting a multi-bit word in a digital memory at a selected address receives a word reset signal to cause entry into the selected address of a multi-bit word wherein all the bits are set to the same level and a parity bit is set to a value corresponding to parity in the multi-bit word. The circuit includes a parity generator which receives a multi-bit input data word and generates at least one parity bit therefrom. During a normal write operation, the multi-bit input data word and the parity bit are written into the digital memory at the selected address. During a word reset signal, output from the parity generator and the multi-bit input data word are blocked from entry into the memory.

Abstract: A reset circuit for a CMOS memory array is disclosed wherein the voltage supply for the standard six transistor memory cell is replaced by a pair of parallel connected transistors disposed between a fixed voltage source and the memory cell. The transistors are controlled by the reset signal and are complementary in that one is n-channel and the other is p-channel. The n-channel transistor is sized to prevent excess current flow to the memory cells to prevent an excessive charge build up therein for a logical "1" representation. In addition, the n-channel transistor provides a Vtn drop thereacross to prevent current flow in the memory cells during reset.

Abstract: A solid state memory system is arranged in a plurality of blocks of memory cells, the memory cells in each block arranged in columns and rows. When the memory system is addressed for a memory reference, block selection circuitry selects one block of the plurality of blocks, excluding all of the other blocks. Each block has a set of sense amplifiers, corresponding in number to the number of bits in the output word. Each sense amplifier is connected to an isolation switch. The outputs from the sense amplifiers connected to the non-selected blocks are thereby isolated from the sense amplifier outputs from the selected block to minimize loading of the sense amplifier outputs from the selected block. The memory cells in each block are interconnected by metal row conductors and by metal column conductors.

Abstract: The disclosure relates to a cache memory formed on a single chip wherein the ability to test the address comparator, cache memory diagnostics are improved, cache memory are capable of being read out. The architecture comprises a parity generator, a parity checker, a comparator and an SRAM memory cell array. The cache memory is cascadable for access to an increased address range and to provide increased memory capacity.

Abstract: A CMOS output pair provides rapid switching speed while avoiding excessive noise levels developed across the power supply parasitic inductance. Both the P-channel and N-channel transistors of the output pair actually comprise a plurality of sub-transistors with their source to drain current paths connected in parallel. As a result of novel RC coupling of a switching signal from gate to gate of either of the plurality of sub-transistors, the sub-transistors are caused to turn on sequentially. Since none of the sub-transistors is capable of supporting the current that must be carried by the totality of sub-transistors making up either the P-channel or N-channel transistor, the increments of current as each sub-transistor turns on are small relative to the total.