Abstract: A first series of memory access transactions are received from a first set of compressed data having a number of first transactions indeterminate in a transaction receiver, and a second series of memory access transactions are received from a second set of compressed data having a number of second transactions indeterminate in the transaction receiver. A count of outstanding transactions for the combined first and second sets of compressed data is received in the transaction receiver, and memory space is allocated for the first and second series of transactions based at least in part on the received count of outstanding combined transactions. The first series of transactions are stored sequentially from a first end of the allocated memory space and the second series of transactions are stored sequentially from a second end of the allocated memory space opposite the first end.

Abstract: Apparatuses, systems, methods, computer-readable media, and computer code are disclosed. An apparatus comprises transaction circuitry configured to control transactions, wherein a configuration of each transaction is controlled by a corresponding unit of configuration data; and a configuration cache configured to hold a plurality of units of configuration data. Each transaction specifies a storage location in the configuration cache at which the corresponding unit of configuration data is stored, and the transaction circuitry is configured to access the corresponding unit of configuration data at the storage location to control each transaction.

Abstract: Apparatuses, systems, methods, computer-readable media, and computer code are disclosed. An apparatus comprises transaction circuitry configured to control transactions, wherein a configuration of each transaction is controlled by a corresponding unit of configuration data; and a configuration cache configured to hold a plurality of units of configuration data. Each transaction specifies a storage location in the configuration cache at which the corresponding unit of configuration data is stored, and the transaction circuitry is configured to access the corresponding unit of configuration data at the storage location to control each transaction.

Abstract: A first series of memory access transactions are received from a first set of compressed data having a number of first transactions indeterminate in a transaction receiver, and a second series of memory access transactions are received from a second set of compressed data having a number of second transactions indeterminate in the transaction receiver. A count of outstanding transactions for the combined first and second sets of compressed data is received in the transaction receiver, and memory space is allocated for the first and second series of transactions based at least in part on the received count of outstanding combined transactions. The first series of transactions are stored sequentially from a first end of the allocated memory space and the second series of transactions are stored sequentially from a second end of the allocated memory space opposite the first end.