Abstract: This asynchronous processor core comprises a loading unit for sequentially loading instruction lines, functional units for executing instructions and a decoder for decoding instruction lines loaded by the loading unit into instructions executable by the functional units. It comprises an execution control module configured as a two-state automaton: a sleep state (S1), wherein the asynchronous processor core awaits an interrupt control signal to execute an interrupt routine; an execution state (S2), wherein the decoder awaits a new interrupt routine instruction line to be decoded. The execution control module additionally manages a state variable (status) of the loading unit to selectively authorize or prevent, according to at least the value of this state variable (status), the loading of a new instruction line.

Abstract: The invention concerns a circuit comprising: a processing circuit (102) comprising a plurality of circuit domains (103), each circuit domain (103) comprising a plurality of transistors and being configured to apply one or more corresponding transistor biasing voltages to said transistors; and a control circuit (104) configured to determine, based on at least a selected accuracy setting of the processing circuit, the level of said one or more transistor biasing voltages to be applied in each of said circuit domains, the control circuit (104) being further configured to cause said transistor biasing voltages to be applied to the circuit domains.

Abstract: An asynchronous circuit including an asynchronous pipeline including two or more stages, each stage having: a buffering circuit for temporarily storing data to be transferred from one stage to the next based on a handshake protocol, the buffering circuit including a non-volatile memory; and a data presence detection circuit adapted to generate a data presence detection value indicating whether or not data is stored by the buffering circuit; and a control circuit adapted to perform a data back-up operation by independently controlling each buffering circuit to back-up the data it stores to its non-volatile memory based on the corresponding data presence detection value.

Abstract: The invention concerns a method of determining the effect of aging on a propagation delay in a circuit path of a digital circuit, the method comprising determining, by a processing device (104) of the digital circuit based on a parameter aging model (?pvth) representing a variation of a first parameter (p) as a function of at least the age of the digital circuit, a variation of the first parameter due to aging at a time t after fabrication of the digital circuit, wherein the first parameter (p) is a parameter of a delay model (DELAY MODEL) representing the propagation delay in the circuit path.

Abstract: The invention concerns a circuit comprising: a processing circuit (102) comprising a plurality of circuit domains (103), each circuit domain (103) comprising a plurality of transistors and being configured to apply one or more corresponding transistor biasing voltages to said transistors; and a control circuit (104) configured to determine, based on at least a selected accuracy setting of the processing circuit, the level of said one or more transistor biasing voltages to be applied in each of said circuit domains, the control circuit (104) being further configured to cause said transistor biasing voltages to be applied to the circuit domains.

Abstract: This asynchronous processor core comprises a loading unit for sequentially loading instruction lines, functional units for executing instructions and a decoder for decoding instruction lines loaded by the loading unit into instructions executable by the functional units. It comprises an execution control module configured as a two-state automaton: a sleep state (S1), wherein the asynchronous processor core awaits an interrupt control signal to execute an interrupt routine; an execution state (S2), wherein the decoder awaits a new interrupt routine instruction line to be decoded. The execution control module additionally manages a state variable (status) of the loading unit to selectively authorize or prevent, according to at least the value of this state variable (status), the loading of a new instruction line.

Abstract: An asynchronous circuit including an asynchronous pipeline including two or more stages, each stage having: a buffering circuit for temporarily storing data to be transferred from one stage to the next based on a handshake protocol, the buffering circuit including a non-volatile memory; and a data presence detection circuit adapted to generate a data presence detection value indicating whether or not data is stored by the buffering circuit; and a control circuit adapted to perform a data back-up operation by independently controlling each buffering circuit to back-up the data it stores to its non-volatile memory based on the corresponding data presence detection value.

Abstract: A method for controlling an electronic circuit by means of the first, second and third operating parameters, comprises: determining a range of variation of the third parameter for each value of the first parameter by varying the second parameter, said ranges being different; determining a target value of the third parameter; if the target value is within one of the ranges, operating the electronic circuit by setting the third parameter to the target value; and in the opposite case, selecting the two ranges framing the target value and operating the electronic circuit by consecutively bringing the third parameter into each one of the selected ranges.

Abstract: The invention concerns a circuit comprising: a C-element having first and second input nodes and first and second inverters (110, 112) cross-coupled between first and second complementary storage nodes (Q, Z), the second storage node (Z) forming an output node of the C-element; and a non-volatile memory comprising: a first resistive element (202) having a first terminal coupled to the first storage node (Q); a second resistive element (204) having a first terminal coupled to the second storage node (Z), at least one of the first and second resistive elements being programmable to have one of at least two resistive states (Rmin, Rmax), wherein a second terminal of the first resistive element (202) is coupled to a second terminal of the second resistive element (204) via a first transistor (210); and a control circuit (232).

Abstract: A method for controlling an electronic circuit by means of the first, second and third operating parameters, comprises: determining a range of variation of the third parameter for each value of the first parameter by varying the second parameter, said ranges being different; determining a target value of the third parameter; if the target value is within one of the ranges, operating the electronic circuit by setting the third parameter to the target value; and in the opposite case, selecting the two ranges framing the target value and operating the electronic circuit by consecutively bringing the third parameter into each one of the selected ranges.

Abstract: The invention concerns a circuit comprising: a C-element having first and second input nodes and first and second inverters (110, 112) cross-coupled between first and second complementary storage nodes ( Q, Z), the second storage node (Z) forming an output node of the C-element; and a non-volatile memory comprising: a first resistive element (202) having a first terminal coupled to the first storage node ( Q); a second resistive element (204) having a first terminal coupled to the second storage node (Z), at least one of the first and second resistive elements being programmable to have one of at least two resistive states (Rmin, Rmax), wherein a second terminal of the first resistive element (202) is coupled to a second terminal of the second resistive element (204) via a first transistor (210); and a control circuit (232).

Abstract: A device for powering an electronic circuit that applies at least a first voltage or a second voltage, different from the first voltage, to the electronic circuit. The device includes a performance monitor that receives an item of information defining a constraint and determines a first duration and a second duration, such that the operation of the electronic circuit at a first frequency associated with the first voltage for the first duration, and at a second frequency associated with the second voltage for the second duration, complies with the constraint. The device applies the first voltage and the first frequency to the circuit for the first duration and the second voltage and the second frequency for the second duration.

Abstract: A system comprising: an electronic circuit exhibiting, in operation, a value v of an operating physical quantity; a measurement device comprising: sensors embedded in the electronic circuit so as to provide raw measurements {Xm} sensitive to the value v of the operating physical quantity, and an output unit for providing useful measurements {X?n} on the basis of the raw measurements {Xm}; a distribution calculation device for determining a current distribution function F(x) associated with the useful measurements {X?n}; a memory wherein associations {Ak} are saved, each association Ak associating a model distribution function Fk(x) with a model value v*k of the operating physical quantity; and an estimation calculation device for determining an estimation {tilde over (v)} of the value v of the operating physical quantity on the basis of the current distribution function F(x) and at least a portion of the saved associations {Ak}.

Abstract: An electronic circuit power supply device configured to selectively apply at least one first voltage or one second voltage to a power supply terminal of the electronic circuit that includes elements for applying to the power supply terminal a voltage variable from a value equal to the first voltage to a value equal to the second voltage and elements designed for selecting application of the second voltage to the power supply terminal when the variable voltage reaches the second voltage.

Abstract: This invention relates to the domain of Networks on Chips (NoC) and relates to a method of transferring data in a network on chip, particularly using an asynchronous “send/accept” type protocol. The invention also relates to a network on chip used to implement this method.

Abstract: A network and a data transmission method between elements in such a network using an asynchronous communication protocol of the “send/accept” type. At least one node in the network operations without an internal clock, this node determining a transfer hierarchy between two data packets to be routed to the same output, at least as a function of a priority channel information associated with each data packet.

Abstract: A device for powering an electronic circuit that applies at least a first voltage or a second voltage, different from the first voltage, to the electronic circuit. The device includes a performance monitor that receives an item of information defining a constraint and determines a first duration and a second duration, such that the operation of the electronic circuit at a first frequency associated with the first voltage for the first duration, and at a second frequency associated with the second voltage for the second duration, complies with the constraint. The device applies the first voltage and the first frequency to the circuit for the first duration and the second voltage and the second frequency for the second duration.

Abstract: An electronic circuit power supply device configured to selectively apply at least one first voltage or one second voltage to a power supply terminal of the electronic circuit that includes elements for applying to the power supply terminal a voltage variable from a value equal to the first voltage to a value equal to the second voltage and elements designed for selecting application of the second voltage to the power supply terminal when the variable voltage reaches the second voltage.

Abstract: The invention relates to a method for exchanging information by inductive coupling or without contact between a reader (2) and a transponder (4), comprising a number of demodulation steps, by the transponder, of a transmission signal coming from the reader, each demodulation step being associated with: a detection of a jump of a parameter of the transmission signal, of a first state to a second state among a set of stable states that the parameter of the transmission signal is capable of adopting; a comparison of the magnitude of the jump and/or of the direction of the jump, at one or more predetermined threshold values; an association with the magnitude of the jump and/or with the direction of the jump, at a value independent of the first state, and; a detection of a stabilization at the second state before another demodulation. The invention also relates to a device for carrying out said method.

Abstract: The invention concerns a radiation detection device comprising a plurality of detector elements (DET1, DET2), each detector element (DET1) being associated with a circuit (AMP1-CMP1) for acquiring pulse signals (H1) and for counting (CNT1) detection events. The invention provides for means (COR) of correlating detection events corresponding to at least two detector elements (DET1/DET2).