Patents by Inventor Edith Kussener

Edith Kussener has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9134191
    Abstract: A resistive device which includes at least one strain gauge (12, 14) comprising silicon nanowires, a power supply (16) that has at least one current source (22, 24) able to generate a current (Ibias) for biasing the strain gauge; and acquisition means (18) able to deliver a measurement signal which can be used to determine the variation in the electrical resistance of the gauge is provided. The power supply includes a chopper (26) allowing the biasing current generated by each current source to flow through each gauge only during a fraction of an operating cycle of the device.
    Type: Grant
    Filed: June 29, 2012
    Date of Patent: September 15, 2015
    Assignees: Centre National de la Recherche Scientifique, Universite Du Sud-toulon Var, Universite D'Aix-Marseille
    Inventors: Wenceslas Rahajandraibe, Stéphane Meillere, Edith Kussener, Hervé Barthelemy
  • Publication number: 20140290376
    Abstract: A resistive device includes at least one strain gauge (12, 14) comprising silicon nanowires, a power supply (16) that has at least one current source (22, 24) able to generate a current (Ibias) for biasing the strain gauge; and acquisition means (18) able to deliver a measurement signal which can be used to determine the variation in the electrical resistance of the gauge. The power supply includes a chopper (26) allowing the biasing current generated by each current source to flow through each gauge only during a fraction of an operating cycle of the device.
    Type: Application
    Filed: June 29, 2012
    Publication date: October 2, 2014
    Applicants: Centre National de la Recherche Scientifique, Universite D'Aix-Marseille, Universite Du Sud-Tulon Var
    Inventors: Wenceslas Rahajandraibe, Stephane Melillere, Edith Kussener, Herve Barthelemy
  • Patent number: 7375502
    Abstract: A method and a circuit for scrambling the current signature of a load comprising at least one integrated circuit executing digital processings, including supplying at least the integrated circuit from a supply voltage external to the circuit by combining a current provided by a first linear regulator with a current provided by at least one capacitive switched-mode power supply circuit with one or several switched capacitances.
    Type: Grant
    Filed: February 7, 2006
    Date of Patent: May 20, 2008
    Assignees: STMicroelectronics S.A., Universite D.Aix-Marseille I
    Inventors: Alexandre Malherbe, Edith Kussener, Vincent Telandro
  • Patent number: 7365523
    Abstract: A method and a circuit for scrambling the current signature of a load including at least one integrated circuit executing digital processings, including the step of, at least on the load ground side, combining a current absorbed by a first linear regulator with a current absorbed by at least one capacitive switched-mode circuit with one or several switched capacitances.
    Type: Grant
    Filed: February 7, 2006
    Date of Patent: April 29, 2008
    Assignee: STMicroelectronics S.A.
    Inventors: Alexandre Malherbe, Edith Kussener, Vincent Telandro
  • Publication number: 20060279366
    Abstract: A method and a circuit for generating a pseudo-random digital flow comprising an oscillator, the biasing of which is controllable by an analog bias source controlled by a signal with continuous amplitude and time variatons.
    Type: Application
    Filed: May 25, 2006
    Publication date: December 14, 2006
    Inventors: Edith Kussener, Vincent Telandro, Fabien Chaillan
  • Publication number: 20060176032
    Abstract: A method and a circuit for scrambling the current signature of a load comprising at least one integrated circuit executing digital processings, including supplying at least the integrated circuit from a supply voltage external to the circuit by combining a current provided by a first linear regulator with a current provided by at least one capacitive switched-mode power supply circuit with one or several switched capacitances.
    Type: Application
    Filed: February 7, 2006
    Publication date: August 10, 2006
    Applicants: STMicroelectronics S.A., Universite D'Aix-Marseille I
    Inventors: Alexandre Malherbe, Edith Kussener, Vincent Telandro
  • Publication number: 20060176033
    Abstract: A method and a circuit for scrambling the current signature of a load including at least one integrated circuit executing digital processings, including the step of, at least on the load ground side, combining a current absorbed by a first linear regulator with a current absorbed by at least one capacitive switched-mode circuit with one or several switched capacitances.
    Type: Application
    Filed: February 7, 2006
    Publication date: August 10, 2006
    Applicants: STMicroelectronics S.A., Universite D'Aix-Marseille I
    Inventors: Alexandre Malherbe, Edith Kussener, Vincent Telandro
  • Patent number: 6465997
    Abstract: A regulated voltage generator provides different regulated voltages to an integrated circuit. The regulated voltage generator includes a bandgap reference circuit and at least one gain stage connected to an output thereof. The output voltage of the bandgap reference circuit varies as a function of temperature to compensate for variations in the gain stage made up of first and second transistors. A regulated voltage output by the regulated voltage generator is independent of temperature and of the supply voltage. The value of the regulated voltage is adjusted via a load resistor and via the first and second transistors along with an output transistor of the bandgap reference circuit.
    Type: Grant
    Filed: September 14, 2001
    Date of Patent: October 15, 2002
    Assignee: STMicroelectronics S.A.
    Inventor: Edith Kussener
  • Publication number: 20020109491
    Abstract: A regulated voltage generator provides different regulated voltages to an integrated circuit. The regulated voltage generator includes a bandgap reference circuit and at least one gain stage connected to an output thereof. The output voltage of the bandgap reference circuit varies as a function of temperature to compensate for variations in the gain stage made up of first and second transistors. A regulated voltage output by the regulated voltage generator is independent of temperature and of the supply voltage. The value of the regulated voltage is adjusted via a load resistor and via the first and second transistors along with an output transistor of the bandgap reference circuit.
    Type: Application
    Filed: September 14, 2001
    Publication date: August 15, 2002
    Applicant: STMicroelectronics S.A.
    Inventor: Edith Kussener