Abstract: A data processing system is provided having a clock signal comparator comprising a reference input port for receiving a reference clock signal and at least a further input port for receiving respective further clock signal. Checking logic is provided within the clock signal comparator to check for a correspondence between the clock edge of the reference clock signal and a corresponding clock edge of the further clock signal within a predetermined time window. The checking logic is operable to check for the correspondence during operation of the data processing system. The clock-signal comparator can be provided on an integrated circuit or as part of the data processing apparatus having at least two different timing domains such as timing domains associated with two different instances of the same clock.

Abstract: A data processing apparatus and method for generating trace elements is provided. The data processing apparatus comprises a device for performing a sequence of operations including memory operations on data values having associated data addresses. For at least some of the memory operations the data address is determined relative to an architectural state value of an item of architectural state of the device. Trace logic is provided for receiving indications of the sequence of operations being performed by the device, and for generating from the indications a stream of trace elements. When for a memory operation the data address is determined to have been determined relative to an architectural state value of the item of the architectural state, the trace logic is operable dependent on that item of architectural state to omit at least one of a data address indication and a data value indication from the stream of trace elements generated in respect of that memory operation.

Abstract: Within an integrated circuit 2 independently controllable domains 4, 6, 8, 10, 12, 14 may be unable to complete pending transactions taking place between domains. Each domain is provided with a state machine 20, 22 which is responsive to the state of the state machine within the other domain and when this indicates that the other domain is not communicating triggers modified behaviour. This can provide that the predetermined transaction protocol is not broken and/or complete a partially completed transaction when the domain concerned has recovered from an error or other event which disrupted the communication.

Abstract: A method, system and unit for controlling the configuration of a transmission path coupling a first unit and a second unit is disclosed. The first unit and the second unit are configurable to support the transfer of information items over the transmission path in time-slots of successive transmission frames in accordance with a plurality of modes, each of the plurality of modes allocating differing numbers of time-slots within each frame to different types of information items.

Abstract: An integrated circuit is provided with diagnostic circuitry, such as serial scan chains or debug bus access circuits, with which communication is established using an interface circuit coupled with a bi-directional serial link to an external diagnostic device. The bi-directional serial link carries both data and control signals.