Abstract: An integrated circuit 2 comprises a functional circuit 4, 6 which is arranged to operate in response to an operational clock signal having an operational clock frequency. To conserve power, the clock signal is distributed across the integrated circuit 2 at a distribution clock frequency which is less than the operational clock frequency. A clock converter 10 is provided to convert the distribution clock signal into the operational clock signal for controlling operation of the functional circuit 4, 6.

Abstract: A trace module generates timestamps while tracing characteristics of a data processing apparatus or processing is performed by the data processing apparatus. When a predetermined event occurs, a timestamp request flag is set to indicate that a timestamp request is pending. Upon generation of a following trace packet, it is determined whether the timestamp request flag indicates that a timestamp request is pending, and if a request is pending then a timestamp is generated corresponding to the following trace packet, and the timestamp request flag is set to indicate that there is no pending timestamp request.

Abstract: A data processing apparatus is disclosed including trace logic for monitoring behavior of a portion of said data processing apparatus and prediction logic for providing at least one prediction as to at least one step of the behavior of the portion of the data processing apparatus. The trace logic monitors behavior of the portion of the data processing apparatus, determines from the monitored behavior whether the at least one prediction is correct, and outputs a prediction indicator indicating whether the at least one prediction is correct.

Abstract: An integrated circuit 300 includes a functional circuit 310 and a diagnostic circuit 330. The integrated circuit includes a signal interface controller 320 operable to monitor a signal associated with at least one of the functional circuit and the diagnostic circuit to control selective communication of a diagnostic signal and a functional signal for communication across a signal interface in dependence upon the monitored signal. A further integrated circuit has a signal interface providing a communication path and communicates a functional signal having at least one multi-bit value in which at least one bit is replaced by data of a diagnostic signal.

Abstract: An integrated circuit 2 comprises a functional circuit 4, 6 which is arranged to operate in response to an operational clock signal having an operational clock frequency. To conserve power, the clock signal is distributed across the integrated circuit 2 at a distribution clock frequency which is less than the operational clock frequency. A clock converter 10 is provided to convert the distribution clock signal into the operational clock signal for controlling operation of the functional circuit 4, 6.

Abstract: A direct memory access controller for controlling data transfer between a plurality of data sources and a plurality of data destinations is disclosed. The plurality of data sources and data destinations communicate with the direct memory access controller via a plurality of channels, the direct memory access controller further communicates with a memory and a processor. The memory stores two sets of control data for each of the plurality of channels and for the processor. The direct memory access controller is responsive to a data transfer request received from one of said plurality of channels or from said processor to access one set of said corresponding control data stored in said memory, said direct memory access performing at least a portion of said data transfer requested in dependence upon said accessed control data.

Abstract: An integrated circuit 300 includes a functional circuit 310 and a diagnostic circuit 330. The integrated circuit includes a signal interface controller 320 operable to monitor a signal associated with at least one of the functional circuit and the diagnostic circuit to control selective communication of a diagnostic signal and a functional signal for communication across a signal interface in dependence upon the monitored signal. A further integrated circuit has a signal interface providing a communication path and communicates a functional signal having at least one multi-bit value in which at least one bit is replaced by data of a diagnostic signal.

Abstract: An integrated circuit 300 includes a functional circuit 310 and a diagnostic circuit 330. The integrated circuit includes a signal interface controller 320 operable to monitor a signal associated with at least one of the functional circuit and the diagnostic circuit to control selective communication of a diagnostic signal and a functional signal for communication across a signal interface in dependence upon the monitored signal. A further integrated circuit has a signal interface providing a communication path and communicates a functional signal having at least one multi-bit value in which at least one bit is replaced by data of a diagnostic signal.

Abstract: A data processing apparatus and method for generating trace elements is provided. The data processing apparatus comprises a device for performing a sequence of operations including memory operations on data values having associated data addresses. For at least some of the memory operations the data address is determined relative to an architectural state value of an item of architectural state of the device. Trace logic is provided for receiving indications of the sequence of operations being performed by the device, and for generating from the indications a stream of trace elements. When for a memory operation the data address is determined to have been determined relative to an architectural state value of the item of the architectural state, the trace logic is operable dependent on that item of architectural state to omit at least one of a data address indication and a data value indication from the stream of trace elements generated in respect of that memory operation.

Abstract: The present invention relates to the field of data processing, in particular, a method, apparatus 1 and trace module 12 for generating timestamps while tracing characteristics of a data processing apparatus or processing being performed by the data processing apparatus. When a predetermined event occurs, a timestamp request flag 18 is set to indicate that a timestamp request is pending. Upon generation of a following trace packet, it is determined whether the timestamp request flag indicates that a timestamp request is pending, and if a request is pending then a timestamp is generated corresponding to the following trace packet, and the timestamp request flag is set to indicate that there is no pending timestamp request.

Abstract: A data processing apparatus is provided with packing circuitry 130 arranged to receive said source data elements from said trace data receiver and applies a packing protocol to said source data elements to pack data of source data elements of a source trace stream into a packed trace data stream for supply to trace accepting circuitry in a format comprising acceptance data elements. The acceptance data elements have a bit-length that is not a factor of the source data element bit-length. In some arrangements the source data elements are non byte-sized data elements. In alternative arrangements, the packing circuitry packs a first positive integer number of source data elements into a data chunk comprising a second, different positive integer number of acceptance data elements.

Abstract: A system is described having a JTAG diagnostic unit and a serial wire diagnostic unit. A watcher unit is connected to a data connection shared between the diagnostic units. Special patterns detected upon the shared data connection serve to switch between diagnostic modes with respective ones of the diagnostic units becoming active.

Abstract: A direct memory access controller for controlling data transfer between a plurality of data sources and a plurality of data destinations is disclosed. The plurality of data sources and data destinations communicate with the direct memory access controller via a plurality of channels, the direct memory access controller further communicates with a memory and a processor. The memory stores two sets of control data for each of the plurality of channels and for the processor. The direct memory access controller is responsive to a data transfer request received from one of said plurality of channels or from said processor to access one set of said corresponding control data stored in said memory, said direct memory access performing at least a portion of said data transfer requested in dependence upon said accessed control data.

Abstract: Within an integrated circuit (2) independently controllable domains (4, 6, 8, 10, 5 12, 14) may be unable to complete pending transactions taking place between domains. Each domain is provided with a state machine (20, 22) which is responsive to the state of the state machine within the other domain and when this indicates that the other domain is not communicating triggers modified behavior. This can provide that the predetermined transaction protocol is not broken and/or complete a partially completed transaction when the domain concerned has recovered from an error or other event which disrupted the communication.

Abstract: A direct memory access controller for controlling data transfer between a plurality of data sources and a plurality of data destinations is disclosed. The plurality of data sources and data destinations communicate with the direct memory access controller via a plurality of channels, the direct memory access controller further communicates with a memory and a processor. The memory stores two sets of control data for each of the plurality of channels and for the processor. The direct memory access controller is responsive to a data transfer request received from one of said plurality of channels or from said processor to access one set of said corresponding control data stored in said memory, said direct memory access performing at least a portion of said data transfer requested in dependence upon said accessed control data.

Abstract: A data processing apparatus is disclosed including trace logic for monitoring behaviour of a portion of said data processing apparatus and prediction logic for providing at least one prediction as to at least one step of the behavior of the portion of the data processing apparatus. The trace logic monitors behavior of the portion of the data processing apparatus, determines from the monitored behaviour whether the at least one prediction is correct, and outputs a prediction indicator indicating whether the at least one prediction is correct.

Abstract: An apparatus for processing data includes diagnostic mechanisms for providing watch point and breakpoint functionality. Semaphores are associated with the watch points and are provided with hardware support within the diagnostic circuitry serving to monitor whether or not accesses to watch point data is being made in accordance with the permissions set up and noted in the semaphore data.

Abstract: A system is described having a JTAG diagnostic unit and a serial wire diagnostic unit. A watcher unit is connected to a data connection shared between the diagnostic units. Special patterns detected upon the shared data connection serve to switch between diagnostic modes with respective ones of the diagnostic units becoming active.

Abstract: A data processing apparatus is disclosed comprising: trace logic for monitoring behavior of a portion of said data processing apparatus; and prediction logic operable to provide at least one prediction as to at least one step of said behavior of said portion of said data processing apparatus; wherein said trace logic is operable to: monitor behavior of said portion of said data processing apparatus; determine from said monitored behavior whether or not said at least one prediction is correct; and output a prediction indicator indicating whether or not said at least one prediction is correct.

Abstract: A system is described having a JTAG diagnostic unit and a serial wire diagnostic unit. A watcher unit is connected to a data connection shared between the diagnostic units. Special patterns detected upon the shared data connection serve to switch between diagnostic modes with respective ones of the diagnostic units becoming active.