Abstract: An automated process identifies which components that retain their state need to be resettable in a design. The design is analyzed to identify components that retain their state and are non-resettable. A set of simulation tests is run on the design, where each test is known to pass when all components that retain their state are reset at reset. The tests are run with a respective logic value (1 or 0) randomly assigned to each non-resettable component at reset, until a test run fails. The failed test is rerun a specified number of times, each time with a different set of randomly assigned logic values provided to non-resettable components at reset. For each run, statistics are logged for each non-resettable component according to the test results and the logic value provided to the non-resettable component. The process determines which non-resettable components need to be resettable according to the statistics.

Abstract: A hardware emulation system may emulate a plurality of cycles of a circuit, and may store state information at each cycle which specifies signal values for one or more signals of the circuit. After the hardware emulation has finished, the state information may be streamed from the memory of the hardware emulation system to a different storage device that is accessible by a computer system that executes one or more software checker routines. The computer system may execute the software checker routines, which may include passing the signal values specified in the state information to the software checker routines on a cycle-by-cycle basis similarly as if the software checker routines were receiving them in real time directly from the hardware emulation system.

Abstract: An automated process identifies which components that retain their state need to be resettable in a design. The design is analyzed to identify components that retain their state and are non-resettable. A set of simulation tests is run on the design, where each test is known to pass when all components that retain their state are reset at reset. The tests are run with a respective logic value (1 or 0) randomly assigned to each non-resettable component at reset, until a test run fails. The failed test is rerun a specified number of times, each time with a different set of randomly assigned logic values provided to non-resettable components at reset. For each run, statistics are logged for each non-resettable component according to the test results and the logic value provided to the non-resettable component. The process determines which non-resettable components need to be resettable according to the statistics.