Patents by Inventor Edmond R. Ward

Edmond R. Ward has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190305047
    Abstract: A re-writeable non-volatile memory device including a re-writeable non-volatile two-terminal memory element (ME) having tantalum. The ME including a first terminal, a second terminal, a first layer of a conductive metal oxide (CMO), and a second layer in direct contact with the first layer. The second layer and the first layer being operative to store at least one-bit of data as a plurality of resistive states, and the first and second layer are electrically in series with each other and with the first and second terminals.
    Type: Application
    Filed: May 14, 2019
    Publication date: October 3, 2019
    Inventors: Christophe J. CHEVALLIER, Steve Kuo-Ren HSIA, Wayne KINNEY, Steven LONGCOR, Darrell RINERSON, John SANCHEZ, Philip F.S. SWAB, Edmond R. WARD
  • Patent number: 10340312
    Abstract: A re-writeable non-volatile memory device including a re-writeable non-volatile two-terminal memory element (ME) having tantalum. The ME including a first terminal, a second terminal, a first layer of a conductive metal oxide (CMO), and a second layer in direct contact with the first layer. The second layer and the first layer being operative to store at least one-bit of data as a plurality of resistive states, and the first and second layer are electrically in series with each other and with the first and second terminals.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: July 2, 2019
    Assignee: Hefei Reliance Memory Limited
    Inventors: Christophe J. Chevallier, Steve Kuo-Ren Hsia, Wayne Kinney, Steven Longcor, Darrell Rinerson, John Sanchez, Philip F. S. Swab, Edmond R. Ward
  • Publication number: 20180122857
    Abstract: A re-writeable non-volatile memory device including a re-writeable non-volatile two-terminal memory element (ME) having tantalum. The ME including a first terminal, a second terminal, a first layer of a conductive metal oxide (CMO), and a second layer in direct contact with the first layer. The second layer and the first layer being operative to store at least one-bit of data as a plurality of resistive states, and the first and second layer are electrically in series with each other and with the first and second terminals.
    Type: Application
    Filed: October 30, 2017
    Publication date: May 3, 2018
    Inventors: Christophe J. Chevallier, Steve Kuo-Ren Hsia, Wayne Kinney, Steven Longcor, Darrell Rinerson, John Sanchez, Philip F.S. Swab, Edmond R. Ward
  • Patent number: 9806130
    Abstract: A re-writeable non-volatile memory device including a re-writeable non-volatile two-terminal memory element (ME) having tantalum. The ME including a first terminal, a second terminal, a first layer of a conductive metal oxide (CMO), and a second layer in direct contact with the first layer. The second layer and the first layer being operative to store at least one-bit of data as a plurality of resistive states, and the first and second layer are electrically in series with each other and with the first and second terminals.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: October 31, 2017
    Assignee: Unity Semiconductor Corporation
    Inventors: Christophe J. Chevallier, Steve Kuo-Ren Hsia, Wayne Kinney, Steven Longcor, Darrell Rinerson, John Sanchez, Philip F. S. Swab, Edmond R. Ward
  • Publication number: 20170179197
    Abstract: A re-writeable non-volatile memory device including a re-writeable non-volatile two-terminal memory element (ME) having tantalum. The ME including a first terminal, a second terminal, a first layer of a conductive metal oxide (CMO), and a second layer in direct contact with the first layer. The second layer and the first layer being operative to store at least one-bit of data as a plurality of resistive states, and the first and second layer are electrically in series with each other and with the first and second terminals.
    Type: Application
    Filed: December 29, 2016
    Publication date: June 22, 2017
    Inventors: Christophe J. Chevallier, Steve Kuo-Ren Hsia, Wayne Kinney, Steven Longcor, Darrell Rinerson, John Sanchez, Philip F.S. Swab, Edmond R. Ward
  • Patent number: 9570515
    Abstract: A memory cell including conductive oxide electrodes is disclosed. The memory cell includes a memory element operative to store data as a plurality of resistive states. The memory element includes a layer of a conductive metal oxide (CMO) (e.g., a perovskite) in contact with an electrode that may comprise one or more layers of material. At least one of those layers of material can be a conductive oxide (e.g., a perovskite such as LaSrCoO3-LSCoO or LaNiO3-LNO) that is in contact with the CMO. The conductive oxide layer can be selected as a seed layer operative to provide a good lattice match with and/or a lower crystallization temperature for the CMO. The conductive oxide layer may also be in contact with a metal layer (e.g., Pt). The memory cell additionally exhibits non-linear IV characteristics, which can be favorable in certain arrays, such as non-volatile two-terminal cross-point memory arrays.
    Type: Grant
    Filed: September 10, 2015
    Date of Patent: February 14, 2017
    Assignee: UNITY SEMICONDUCTOR CORPORATION
    Inventors: Christophe J. Chevallier, Steve Kuo-Ren Hsia, Wayne Kinney, Steven Longcor, Darrell Rinerson, John Sanchez, Philip F. S. Swab, Edmond R. Ward
  • Publication number: 20160005793
    Abstract: A memory cell including conductive oxide electrodes is disclosed. The memory cell includes a memory element operative to store data as a plurality of resistive states. The memory element includes a layer of a conductive metal oxide (CMO) (e.g., a perovskite) in contact with an electrode that may comprise one or more layers of material. At least one of those layers of material can be a conductive oxide (e.g., a perovskite such as LaSrCoO3-LSCoO or LaNiO3-LNO) that is in contact with the CMO. The conductive oxide layer can be selected as a seed layer operative to provide a good lattice match with and/or a lower crystallization temperature for the CMO. The conductive oxide layer may also be in contact with a metal layer (e.g., Pt). The memory cell additionally exhibits non-linear IV characteristics, which can be favorable in certain arrays, such as non-volatile two-terminal cross-point memory arrays.
    Type: Application
    Filed: September 10, 2015
    Publication date: January 7, 2016
    Inventors: Christophe J. Chevallier, Steve Kuo-Ren Hsia, Wayne Kinney, Steven Longcor, Darrell Rinerson, John Sanchez, Philip F.S. Swab, Edmond R. Ward
  • Patent number: 9159408
    Abstract: A memory cell including conductive oxide electrodes is disclosed. The memory cell includes a memory element operative to store data as a plurality of resistive states. The memory element includes a layer of a conductive metal oxide (CMO) (e.g., a perovskite) in contact with an electrode that may comprise one or more layers of material. At least one of those layers of material can be a conductive oxide (e.g., a perovskite such as LaSrCoO3-LSCoO or LaNiO3-LNO) that is in contact with the CMO. The conductive oxide layer can be selected as a seed layer operative to provide a good lattice match with and/or a lower crystallization temperature for the CMO. The conductive oxide layer may also be in contact with a metal layer (e.g., Pt). The memory cell additionally exhibits non-linear IV characteristics, which can be favorable in certain arrays, such as non-volatile two-terminal cross-point memory arrays.
    Type: Grant
    Filed: January 29, 2014
    Date of Patent: October 13, 2015
    Assignee: UNITY SEMICONDUCTOR CORPORATION
    Inventors: Christophe J. Chevallier, Steve Kuo-Ren Hsia, Wayne Kinney, Steven Longcor, Darrell Rinerson, John Sanchez, Philip F. S. Swab, Edmond R. Ward
  • Publication number: 20140211542
    Abstract: A memory cell including conductive oxide electrodes is disclosed. The memory cell includes a memory element operative to store data as a plurality of resistive states. The memory element includes a layer of a conductive metal oxide (CMO) (e.g., a perovskite) in contact with an electrode that may comprise one or more layers of material. At least one of those layers of material can be a conductive oxide (e.g., a perovskite such as LaSrCoO3-LSCoO or LaNiO3-LNO) that is in contact with the CMO. The conductive oxide layer can be selected as a seed layer operative to provide a good lattice match with and/or a lower crystallization temperature for the CMO. The conductive oxide layer may also be in contact with a metal layer (e.g., Pt). The memory cell additionally exhibits non-linear IV characteristics, which can be favorable in certain arrays, such as non-volatile two-terminal cross-point memory arrays.
    Type: Application
    Filed: January 29, 2014
    Publication date: July 31, 2014
    Applicant: Unity Semiconductor Corporation
    Inventors: Christophe J. Chevallier, Steve Kuo-Ren Hsia, Wayne Kinney, Steven Longcor, Darrell Rinerson, John Sanchez, Philip F.S. Swab, Edmond R. Ward
  • Publication number: 20120064691
    Abstract: A treated conductive element is provided. A conductive element can be treated by depositing either a reactive metal or a very thin layer of material on the conductive element. The reactive metal (or very thin layer of material) would typically be sandwiched between the conductive element and an electrode. The structure additionally exhibits non-linear IV characteristics, which can be favorable in certain arrays.
    Type: Application
    Filed: November 21, 2011
    Publication date: March 15, 2012
    Applicant: UNITY SEMICONDUCTOR CORPORATION
    Inventors: DARRELL RINERSON, WAYNE KINNEY, EDMOND R. WARD, STEVE KUO-REN HSIA, STEVEN W. LONGCOR, CHRISTOPHE J. CHEVALLIER, JOHN SANCHEZ, PHILIP F. S. SWAB
  • Publication number: 20120033481
    Abstract: A memory cell including conductive oxide electrodes is disclosed. The memory cell includes a memory element operative to store data as a plurality of resistive states. The memory element includes a layer of a conductive metal oxide (CMO) (e.g., a perovskite) in contact with an electrode that may comprise one or more layers of material. At least one of those layers of material can be a conductive oxide (e.g., a perovskite such as LaSrCoO3—LSCoO or LaNiO3—LNO) that is in contact with the CMO. The conductive oxide layer can be selected as a seed layer operative to provide a good lattice match with and/or a lower crystallization temperature for the CMO. The conductive oxide layer may also be in contact with a metal layer (e.g., Pt). The memory cell additionally exhibits non-linear IV characteristics, which can be favorable in certain arrays, such as non-volatile two-terminal cross-point memory arrays.
    Type: Application
    Filed: October 13, 2011
    Publication date: February 9, 2012
    Applicant: UNITY SEMICONDUCTOR CORPORATION
    Inventors: DARRELL RINERSON, WAYNE KINNEY, EDMOND R. WARD, STEVE KUO-REN HSIA, STEVEN LONGCOR, CHRISTOPHE J. CHEVALLIER, JOHN SANCHEZ, PHILIP F. S. SWAB
  • Publication number: 20110186803
    Abstract: A memory cell including conductive oxide electrodes is disclosed. The memory cell includes a memory element operative to store data as a plurality of resistive states. The memory element includes a layer of a conductive metal oxide (CMO) (e.g., a perovskite) in contact with an electrode that may comprise one or more layers of material. At least one of those layers of material can be a conductive oxide (e.g., a perovskite such as LaSrCoO3-LSCoO or LaNiO3-LNO) that is in contact with the CMO. The conductive oxide layer can be selected as a seed layer operative to provide a good lattice match with and/or a lower crystallization temperature for the CMO. The conductive oxide layer may also be in contact with a metal layer (e.g., Pt). The memory cell additionally exhibits non-linear IV characteristics, which can be favorable in certain arrays, such as non-volatile two-terminal cross-point memory arrays.
    Type: Application
    Filed: February 15, 2011
    Publication date: August 4, 2011
    Applicant: UNITY SEMICONDUCTOR CORPORATION
    Inventors: Darrell Rinerson, Wayne Kinney, Edmond R. Ward, Steve Kuo-Ren Hsia, Steven W. Longcor, Christophe J. Chevallier, John Sanchez, Philip F.S. Swab
  • Publication number: 20100157657
    Abstract: A memory cell including conductive oxide electrodes is disclosed. The memory cell includes a memory element operative to store data as a plurality of resistive states. The memory element includes a layer of a conductive metal oxide (CMO) (e.g., a perovskite) in contact with an electrode that may comprise one or more layers of material. At least one of those layers of material can be a conductive oxide (e.g., a perovskite such as LaSrCoO3-LSCoO or LaNiO3-LNO) that is in contact with the CMO. The conductive oxide layer can be selected as a seed layer operative to provide a good lattice match with and/or a lower crystallization temperature for the CMO. The conductive oxide layer may also be in contact with a metal layer (e.g., Pt). The memory cell additionally exhibits non-linear IV characteristics, which can be favorable in certain arrays, such as non-volatile two-terminal cross-point memory arrays.
    Type: Application
    Filed: December 14, 2009
    Publication date: June 24, 2010
    Applicant: UNITY SEMICONDUCTOR CORPORATION
    Inventors: Darrell Rinerson, Wayne Kinney, Edmond R. Ward, Steve Kuo-Ren Hsia, Steven W. Longcor, Christophe J. Chevallier, John Sanchez, Philip F.S. Swab
  • Publication number: 20090045390
    Abstract: A memory cell including conductive oxide electrodes is disclosed. The memory cell includes a memory element operative to store data as a plurality of resistive states. The memory element includes a layer of a conductive metal oxide (CMO) (e.g., a perovskite) in contact with an electrode that may comprise one or more layers of material. At least one of those layers of material can be a conductive oxide (e.g., a perovskite such as LaSrCoO3—LSCoO or LaNiO3—LNO) that is in contact with the CMO. The conductive oxide layer can be selected as a seed layer operative to provide a good lattice match with and/or a lower crystallization temperature for the CMO. The conductive oxide layer may also be in contact with a metal layer (e.g., Pt). The memory cell additionally exhibits non-linear IV characteristics, which can be favorable in certain arrays, such as non-volatile two-terminal cross-point memory arrays.
    Type: Application
    Filed: October 1, 2008
    Publication date: February 19, 2009
    Applicant: UNITY SEMICONDUCTOR CORPORATION
    Inventors: Darrel Rinerson, Wayne Kinney, Edmond R. Ward, Steve Kuo-Ren Hsia, Steven W. Longcor, Christophe J. Chevallier, John Sanchez, Philip F. S. Swab
  • Publication number: 20080293196
    Abstract: A treated conductive element is provided. A conductive element can be treated by depositing either a reactive metal or a very thin layer of material on the conductive element. The reactive metal (or very thin layer of material) would typically be sandwiched between the conductive element and an electrode. The structure additionally exhibits non-linear IV characteristics, which can be favorable in certain arrays.
    Type: Application
    Filed: June 30, 2008
    Publication date: November 27, 2008
    Applicant: UNITY SEMICONDUCTOR CORPORATION
    Inventors: Darrell Rinerson, Wayne Kinney, Edmond R. Ward, Steve Kuo-Ren Hsia, Steven W. Longcor, Christophe J. Chevallier, John Sanchez, Philip F.S. Swab
  • Patent number: 7180772
    Abstract: A cross point array and peripheral circuitry that accesses the cross point array. The peripheral circuitry receives a supply voltage of approximately 1.8 volts or less, generates voltages of a magnitude not more than approximately 3 volts, and senses current that is indicative of a nonvolatile memory state.
    Type: Grant
    Filed: July 11, 2005
    Date of Patent: February 20, 2007
    Inventors: Darrell Rinerson, Steven W. Longcor, Edmond R. Ward, Wayne Kinney
  • Patent number: 7095643
    Abstract: A re-writable memory with multiple memory layers. Using both terminals of a memory cell in a stacked cross point structure for selection purposes allows multiple layers of conductive lines to be selected as long as there is only one memory cell that has two terminals selected. Sharing logic over multiple layers allows driver sets to be reused.
    Type: Grant
    Filed: June 13, 2005
    Date of Patent: August 22, 2006
    Inventors: Darrell Rinerson, Christophe Chevallier, Wayne Kinney, Steven W. Longcor, Edmond R. Ward
  • Patent number: 7079442
    Abstract: Layouts of driver sets in a cross point memory array. Since both terminals of a memory cell in a cross point structure are typically used for selection purposes, dedicated driver sets are typically required for both x and y directions. By fabricating the cross point array above the driver circuitry, several different driver set layouts can be utilized that allow for varying designs.
    Type: Grant
    Filed: July 1, 2003
    Date of Patent: July 18, 2006
    Inventors: Darrell Rinerson, Christophe J. Chevallier, Steven W. Longcor, Wayne Kinney, Edmond R. Ward
  • Patent number: 7071008
    Abstract: A multi-resistive state material that uses dopants is provided. A multi-resistive state material can be used in a memory cell to store information. However, a multi-resistive state material may not have electrical properties that are appropriate for a memory device. Intentionally doping a multi-resistive state material to modify the electrical properties can, therefore, be desirable.
    Type: Grant
    Filed: August 4, 2003
    Date of Patent: July 4, 2006
    Inventors: Darrell Rinerson, Wayne Kinney, Christophe J. Chevallier, Steven W. Longcor, Edmond R. Ward, Steve Kuo-Ren Hsia
  • Patent number: 7067862
    Abstract: A multi-resistive state element that uses barrier electrodes is provided. If certain materials are used as electrodes, the electrodes can be used for multiple purposes. Oxides and nitrides are especially well suited for acting as a barrier layer, and possibly even an adhesion layer and a sacrificial layer.
    Type: Grant
    Filed: October 8, 2003
    Date of Patent: June 27, 2006
    Inventors: Darrell Rinerson, Steven W. Longcor, Steve Kuo-Ren Hsia, Wayne Kinney, Edmond R. Ward, Christophe J. Chevallier