Abstract: A logic gate is provided that comprises a sensing circuit coupled to a test output and to an internal node of the logic gate. The sensing circuit is adapted to sense a voltage on the internal node and to output a signal indicating a level of the voltage. The sensing circuit is not used during normal operation of the logic gate and preferably comprises only a single FET that is directly coupled to both the internal node and to the test output. The logic gate also preferably comprises a pre-charge circuit for pre-charging the test output to a predetermined voltage level prior to testing. An IC chip may be formed from a plurality of the logic gates wherein each logic gate comprises a sensing circuit coupled to a test output and to an internal node of the logic gate. Each sensing circuit may be coupled to the same test output or to a unique test output for the sensing circuit's logic gate. The sensing circuits are not used during normal operation of the IC chip.

Abstract: An on-chip test circuit for evaluating on-chip signals for a semiconductor memory chip includes an on-chip signal associated with a memory circuit on the chip; said on-chip signal having a signal characteristic to be evaluated; an input circuit for receiving an off-chip test signal; and a test circuit that compares said on-chip signal and said test signal.